Watchdog Timer; General; Wdt Control Status Register (Wcsr); Wdt Keepalive Register (Wkpa) - GE VMIVME-7805 Hardware Reference Manual

3.5 Watchdog Timer

46 VMIVME-7805/VME-7805RC Hardware Reference Manual

3.5.1 General

The VMIVME-7805/VME-7805RC provide a programmable Watchdog Timer
(WDT) which can be used to reset the system if software integrity fails.

3.5.2 WDT Control Status Register (WCSR)

The WDT is controlled and monitored by the WDT Control Status Register
(WCSR) which is located at offset 0x08 from the address in BAR2. The mapping of
the bits in this register are as follows:
Field
SERR/RST Select
WDT Timeout Select
WDT Enable
All of these bits default to "0" after system reset. All other bits are reserved.
The "WDT Timeout Select" field is used to select the timeout value of the
Watchdog Timer as follows:
Timeout WCSR[10]
135s 0
33.6s 0
2.1s 0
524ms 0
262ms 1
131ms 1
32.768ms 1
2.048ms 1
The "SERR/RST Select" bit is used to select whether the WDT generates an SERR#
on the local PCI bus or a system reset. If this bit is set to "0", the WDT will
generate a system reset. Otherwise, the WDT will make the local PCI bus SERR#
signal active.
The "WDT Enable" bit is used to enable the Watchdog Timer function. This bit
must be set to "1" in order for the Watchdog Timer to function. Note that since all
registers default to zero after reset, the Watchdog Timer is always disabled after a
reset. The Watchdog Timer must be re-enabled by the application software after
reset in order for the Watchdog Timer to continue to operate. Once the Watchdog
Timer is enabled, the application software must refresh the Watchdog Timer
within the selected timeout period to prevent a reset or SERR# from being
generated. The Watchdog Timer is refreshed by performing a write to the WDT
Keepalive register (WKPA). The data written is irrelevant.

3.5.3 WDT Keepalive Register (WKPA)

When enabled, the Watchdog Timer is prevented from resetting the system by
writing to the WKPA located at offset 0x0C from the address in BAR2 within the
selected timeout period. The data written to this location is irrelevant.
Bits Read or Write
WCSR[16] Read/Write
WCSR[10..8] Read/Write
WCSR[0] Read/Write
WCSR[9] WCSR[8]
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1