NEC 78K0 Series User Manual page 208

Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (2/3)
(b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI01n pin input)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture & count clear input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
This is a timing example where an edge is not input to the TI00n pin, in an application where the count value is
captured to CR00n when the rising or falling edge of the TI01n pin is detected.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
L
00
0000H
L
0000H
L
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