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matching a CAM entry. This bit is not set if the A indicator is not received or if DA = my
long address register, where my long address register is a group address.
3.3.2 Interrupt Event Register B (INTR_EVENT_B)
15
14
MY_BEACON
OTHER_
BEACON
7
6
WON_CLAIM
NP_ERR
MY_BEACON—My Beacon
This bit is set when the receiver FSM signals the MY_BEACON event. The conditions
that cause the receiver FSM to signal this condition are described in the ANSI FDDI
MAC standard in the MAC receiver FSM text and state diagram. Although the receiver
only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt
remains set until it is read by the external processor.
OTHER_BEACON—Other Beacon
This bit is set when the receiver FSM signals the OTHER_BEACON event. The
conditions that cause the receiver FSM to signal this condition are described in the ANSI
FDDI MAC standard in the MAC receiver FSM text and state diagram. Although the
receiver only asserts this signal for one clock cycle, as with all MAC interrupts, this
interrupt remains set until it is read by the external processor.
HIGHER_CLAIM—Higher Claim
This bit is set when the receiver FSM signals the HIGHER_CLAIM event. The conditions
that cause the receiver FSM to signal this condition are described in the ANSI FDDI
MAC standard in the MAC receiver FSM text and state diagram. Although the receiver
only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt
remains set until it is read by the external processor.
LOWER_CLAIM—Lower Claim
This bit is set when the receiver FSM signals the LOWER_CLAIM event. The conditions
that cause the receiver FSM to signal this condition are described in the ANSI FDDI
MAC standard in the MAC receiver FSM text and state diagram. Although the receiver
only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt
remains set until it is read by the external processor.
MY_CLAIM—My Claim
This bit is set when the receiver FSM signals the MY_CLAIM event. The conditions that
cause the receiver FSM to signal this condition are described in the ANSI FDDI MAC
standard in the MAC receiver FSM text and state diagram. Although the receiver only
asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt remains
set until it is read by the external processor.
3- 20
13
12
HIGHER_
LOWER_CLAIM
CLAIM
5
4
SI_ERR
NOT_COPIED
MC68838 USER'S MANUAL
11
10
MY_CLAIM
BAD_T_BID
3
2
FDX_CHANGE
BIT4_I_SS
9
8
PURGE_ERR
BRIDGE_
STRIP_ERR
1
0
BIT5_I_SS
BAD_CRC_
SENT
MOTOROLA
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