LH79524/LH79525 User's Guide
6.3.3.4 Multiple Collision Frames (MULTFRM)
This register counts the number of frames that experienced between two and 15 collisions
before successful transmission.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:16
15:0
6.3.3.5 Frames Received OK (FRMRXOK)
This is a 24-bit register containing the number of good frames received. Good frames are
defined as having the address recognized and successfully copied to memory. A good
frame length is between 64 and 1,518 bytes (1,522 if NETCONFIG:RECBYTE is 1) and
has no FCS, alignment, or receive symbol errors.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:24
23:0
Table 6-40. MULTFRM Register
31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 6-41. MULTFRM Fields
NAME
///
Reserved Reading returns 0. Write the reset value.
Multiple Collision Frames Contains the number of successfully-
MULTFRM
transmitted frames that experienced between two and 15 collisions.
Table 6-42. FRMRXOK Register
31
30
29
28
27
///
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 6-43. FRMRXOK Fields
NAME
///
Reserved Reading returns 0. Write the reset value.
FRMRXOK
Frames Received OK Number of correctly received frames.
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
MULTFRM
0
0
0
0
RW
RW
RW
RW
0xFFFC7000 + 0x48
FUNCTION
26
25
24
23
0
0
0
0
RO
RO
RO
RW
10
9
8
7
FRMRXOK
0
0
0
0
RW
RW
RW
RW
0xFFFC7000 + 0x4C
FUNCTION
Version 1.0
Ethernet MAC Controller
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
18
FRMRXOK
0
0
0
0
0
RW
RW
RW
RW
RW
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
17
16
0
0
RW
RW
1
0
0
0
RW
RW
6-39