NEC VR4181 mPD30181 Manuals

Manuals and User Guides for NEC VR4181 mPD30181. We have 1 NEC VR4181 mPD30181 manual available for free PDF download: User Manual

NEC VR4181 mPD30181 User Manual (444 pages)

64-/32-Bit Microprocessor Hardware

Brand: NEC | Category: Computer Hardware | Size: 1.49 MB

Table of Contents
13
Chapter 1 Introduction

29
- Features
  
  29
- Ordering Information
  
  30
- R 4181 Key Features
  
  30
  - Internal Block Diagram
    30
    
    CPU Core
    31
    
    Bus Interface
    31
    
    Memory Interface
    32
    
    DMA Controller (DCU)
    32
    
    Interrupt Controller (ICU)
    32
    
    Real-Time Clock
    32
    
    Audio Output (D/A Converter)
    32
    
    Touch Panel Interface and Audio Input (A/D Converter)
    32
    
    Compactflash Interface (ECU)
    32
    
    Serial Interface Channel 1 (SIU1)
    32
    
    Serial Interface Channel 2 (SIU2)
    32
    
    Clocked Serial Interface (CSI)
    33
    
    Keyboard Interface (KIU)
    33
    
    General-Purpose I/O
    33
    
    Programmable Chip Selects
    34
    
    LCD Interface
    34
    
    Wake-Up Events
    35
- R 4110 CPU Core
  
  35
  - R 4110 CPU Core Internal Block Diagram
    35
    
    CPU Registers
    37
    
    CPU Instruction Set Overview
    38
  - CPU Instruction Formats (32-Bit Length Instruction)
    38
  - CPU Instruction Formats (16-Bit Length Instruction)
    39
    
    Data Formats and Addressing
    40
  - Byte Address in Little-Endian Byte Order
    41
  - Unaligned Word Accessing (Little Endian)
    42
    
    CP0 Registers
    43
    
    Floating-Point Unit (FPU)
    44
    
    Memory Management Unit
    44
    
    Cache
    44
    
    Instruction Pipeline
    44
    
    Power Modes
    45
    
    Code Compatibility
    46
- Clock Interface
  
  47
  - External Circuits of Clock Oscillator
    48
  - Incorrect Connection Circuits of Resonator
    49
Chapter 2 Pin Functions

50
- Pin Configuration
  
  50
- Pin Function Description
  
  52
- Pin Status in Specific Status
  
  60
- Recommended Connection of Unused Pins and I/O Circuit Types
  
  63
- Pin I/O Circuits
  
  66
Chapter 3 Cp0 Registers

67
- Coprocessor 0 (CP0)
  
  67
- Details of CP0 Registers
  
  69
  - Index Register
    69
  - Random Register (1)
    69
  - Random Register
    69
    
    Entrylo0 (2) and Entrylo1 (3) Registers
    70
  - Entrylo0 and Entrylo1 Registers
    70
    
    Context Register (4)
    71
  - Context Register
    71
    
    Pagemask Register (5)
    72
  - Pagemask Register
    72
    
    Wired Register
    73
  - Positions Indicated by the Wired Register
    73
    
    Badvaddr Register (8)
    74
    
    Count Register
    74
  - Badvaddr Register
    74
    
    Entryhi Register (10)
    75
  - Entryhi Register
    75
    
    Compare Register (11)
    76
    
    Status Register (12)
    76
  - Compare Register
    76
  - Status Register
    76
  - Status Register Diagnostic Status Field
    77
    
    Cause Register
    79
    
    Exception Program Counter (EPC) Register (14)
    81
  - EPC Register (When MIPS16 ISA Is Disabled)
    81
    
    Processor Revision Identifier (Prid) Register (15)
    82
  - EPC Register (When MIPS16 ISA Is Enabled)
    82
  - Prid Register
    82
    
    Config Register (16)
    83
  - Config Register
    83
    
    Load Linked Address (Lladdr) Register (17)
    84
  - Lladdr Register
    84
    
    Watchlo (18) and Watchhi (19) Registers
    85
  - Watchlo Register
    85
  - Watchhi Register
    85
    
    Xcontext Register (20)
    86
  - Xcontext Register
    86
    
    Parity Error Register (26)
    87
    
    Cache Error Register (27)
    87
  - Parity Error Register
    87
  - Cache Error Register
    87
    
    Taglo (28) and Taghi (29) Registers
    88
  - Taglo Register
    88
  - Taghi Register
    88
    
    Errorepc Register (30)
    89
  - Errorepc Register (When MIPS16 ISA Is Disabled)
    90
  - Errorepc Register (When MIPS16 ISA Is Enabled)
    90
Chapter 4 Memory Management System

91
- Overview
  
  91
- Physical Address Space
  
  92
  - R 4181 Physical Address Space
    92
    
    ROM Space
    93
    
    External System Bus Space
    93
    
    Internal I/O Space
    94
    
    DRAM Space
    95
Chapter 5 Initialization Interface

96
- Reset Function
  
  96
  - RTC Reset
    97
  - RSTSW Reset
    98
  - Deadman's Switch Reset
    99
  - Software Shutdown
    100
  - Haltimer Shutdown
    101
- Power-On Sequence
  
  102
  - R 4181 Activation Sequence (When Activation Is OK)
    102
  - R 4181 Activation Sequence (When Activation Is NG)
    103
- Reset of CPU Core
  
  104
  - Cold Reset
    104
  - Soft Reset
    105
- Notes on Initialization
  
  106
  - CPU Core
    106
  - Internal Peripheral Units
    106
  - Returning from Power Mode
    107
Chapter 6 Bus Control

108
- MBA Host Bridge
  
  108
  - R 4181 Internal Bus Structure
    108
    
    MBA Host Bridge ROM and Register Address Space
    109
    
    MBA Modules Address Space
    109
- Bus Control Registers
  
  110
  - BCUCNTREG1 (0X0A00 0000)
    111
  - CMUCLKMSK (0X0A00 0004)
    112
  - BCUSPEEDREG (0X0A00 000C)
    113
  - ROM Read Cycle and Access Parameters
    114
    
    BCURFCNTREG (0X0A00 0010)
    115
    
    REVIDREG (0X0A00 0014)
    116
    
    CLKSPEEDREG (0X0A00 0018)
    117
- ROM Interface
  
  118
- DRAM Interface
  
  128
  - EDO DRAM Configuration
    128
  - External EDO DRAM Configuration
    128
    
    Mixed Memory Mode (EDO DRAM Only)
    129
    
    EDO DRAM Timing Parameters
    129
    
    SDRAM Configuration
    130
- Memory Controller Register Set
  
  131
  - EDOMCYTREG (0X0A00 0300)
    131
  - MEMCFG_REG (0X0A00 0304)
    133
  - MODE_REG (0X0A00 0308)
    135
  - SDTIMINGREG (0X0A00 030C)
    136
- ISA Bridge Register Set
  
  137
  - ISABRGCTL (0X0B00 02C0)
    138
  - ISABRGSTS (0X0B00 02C2)
    139
  - XISACTL (0X0B00 02C4)
    140
- ISA Bridge
  
  137
Chapter 7 Dma Control Unit (Dcu)

142
- General
  
  142
- DCU Registers
  
  144
  - Microphone Destination 1 Address Registers
    145
  - Microphone Destination 2 Address Registers
    146
  - Speaker Source 1 Address Registers
    147
  - Speaker Source 2 Address Registers
    148
  - DMARSTREG (0X0A00 0040)
    149
  - AIUDMAMSKREG (0X0A00 0046)
    149
  - MICRCLENREG (0X0A00 0658)
    150
  - SPKRCLENREG (0X0A00 065A)
    150
  - MICDMACFGREG (0X0A00 065E)
    151
  - SPKDMACFGREG (0X0A00 0660)
    152
  - DMAITRQREG (0X0A00 0662)
    153
  - DMACTLREG (0X0A00 0664)
    154
  - DMAITMKREG (0X0A00 0666)
    155
Chapter 8 Clocked Serial Interface Unit (Csi)

156
- Overview
  
  156
- Operation of CSI
  
  156
  - Transmit/Receive Operations
    156
  - SCK Phase and CSI Transfer Timing
    157
  - SCK and SI/SO Relationship
    157
    
    CSI Transfer Types
    159
    
    Transmit and Receive Fifos
    160
- CSI Registers
  
  160
  - CSIMODE (0X0B00 0900)
    161
  - CSIRXDATA (0X0B00 0902)
    163
  - CSITXDATA (0X0B00 0904)
    163
  - CSILSTAT (0X0B00 0906)
    164
  - CSIINTMSK (0X0B00 0908)
    166
  - CSIINTSTAT (0X0B00 090A)
    167
  - CSITXBLEN (0X0B00 090C)
    169
  - CSIRXBLEN (0X0B00 090E)
    170
Chapter 9 Interrupt Control Unit (Icu)

171
- Overview
  
  171
  - Outline of Interrupt Control
    172
- Register Set
  
  173
  - SYSINT1REG (0X0A00 0080)
    174
  - MSYSINT1REG (0X0A00 008C)
    176
  - NMIREG (0X0A00 0098)
    178
  - SOFTINTREG (0X0A00 009A)
    179
  - SYSINT2REG (0X0A00 0200)
    180
  - MSYSINT2REG (0X0A00 0206)
    181
  - PIUINTREG (0X0B00 0082)
    182
  - AIUINTREG (0X0B00 0084)
    183
  - KIUINTREG (0X0B00 0086)
    184
  - MPIUINTREG (0X0B00 008E)
    185
  - MAIUINTREG (0X0B00 0090)
    186
  - MKIUINTREG (0X0B00 0092)
    187
Chapter 10 Power Management Unit (Pmu)

188
- General
  
  188
- R 4181 Power Mode
  
  188
  - Power Mode and State Transition
    188
  - R 4181 Power Mode
    189
- Reset Control
  
  191
  - RTC Reset
    191
  - Deadman's Switch Reset
    192
  - EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0)
    192
- Shutdown Control
  
  193
  - Preserving DRAM Data on RSTSW Reset
    192
  - RSTSW Reset
    192
  - BATTINH Shutdown
    193
  - Haltimer Shutdown
    193
  - Software Shutdown
    193
- Power-On Control
  
  194
- DRAM Interface Control
  
  201
  - Entering Hibernate Mode (EDO DRAM)
    201
  - Entering Hibernate Mode (SDRAM)
    202
  - Exiting Hibernate Mode (EDO DRAM)
    203
  - Exiting Hibernate Mode (SDRAM)
    204
  - Entering Suspend Mode (EDO DRAM)
    205
  - Entering Suspend Mode (SDRAM)
    206
  - Exiting Suspend Mode (EDO DRAM)
    207
  - Exiting Suspend Mode (SDRAM)
    207
- Register Set
  
  208
  - PMUINTREG (0X0B00 00A0)
    209
  - PMUCNTREG (0X0B00 00A2)
    211
  - PMUWAITREG (0X0B00 00A8)
    213
  - PMUDIVREG (0X0B00 00AC)
    214
  - DRAMHIBCTL (0X0B00 00B2)
    215
Chapter 11 Realtime Clock Unit (Rtc)

216
- General
  
  216
- Register Set
  
  216
  - Elapsedtime Registers
    217
  - Elapsedtime Compare Registers
    219
  - Rtclong1 Registers
    221
  - Rtclong1 Count Registers
    223
  - Rtclong2 Registers
    225
  - Rtclong2 Count Registers
    227
  - RTC Interrupt Register
    229
Chapter 12 Deadman's Switch Unit (Dsu)

230
- General
  
  230
- Register Set
  
  230
  - DSUCNTREG (0X0B00 00E0)
    231
  - DSUSETREG (0X0B00 00E2)
    232
  - DSUCLRREG (0X0B00 00E4)
    233
  - DSUTIMREG (0X0B00 00E6)
    234
- Register Setting Flow
  
  235
Chapter 13 General Purpose I/O Unit (Giu)

236
- Overview
  
  236
  - GPIO Pins and Alternate Functions
    236
  - I/O Direction Control
    238
  - General-Purpose Registers
    238
- Alternate Functions Overview
  
  238
  - Clocked Serial Interface (CSI)
    238
  - Serial Interface Channels 1 and 2
    239
  - LCD Interface
    241
  - Programmable Chip Selects
    242
  - 16-Bit Bus Cycles
    242
  - General Purpose Input/Output
    242
  - Interrupt Requests and Wake-Up Events
    243
  - GPIO(15:0) Interrupt Request Detecting Logic
    243
- Register Set
  
  244
  - GPMD0REG (0X0B00 0300)
    246
  - GPMD1REG (0X0B00 0302)
    248
  - GPMD2REG (0X0B00 0304)
    250
  - GPMD3REG (0X0B00 0306)
    252
  - GPDATHREG (0X0B00 0308)
    254
  - GPDATLREG (0X0B00 030A)
    255
  - GPINTEN (0X0B00 030C)
    256
  - GPINTMSK (0X0B00 030E)
    257
  - GPINTTYPH (0X0B00 0310)
    258
  - GPINTTYPL (0X0B00 0312)
    260
  - GPINTSTAT (0X0B00 0314)
    262
  - GPHIBSTH (0X0B00 0316)
    263
  - GPHIBSTL (0X0B00 0318)
    264
  - GPSICTL (0X0B00 031A)
    265
  - KEYEN (0X0B00 031C)
    267
  - PCS0STRA (0X0B00 0320)
    268
  - PCS0STPA (0X0B00 0322)
    268
  - PCS0HIA (0X0B00 0324)
    269
  - PCS1STRA (0X0B00 0326)
    270
  - PCS1STPA (0X0B00 0328)
    270
  - PCS1HIA (0X0B00 032A)
    271
  - PCSMODE (0X0B00 032C)
    272
  - LCDGPMODE (0X0B00 032E)
    273
  - Miscregn (0X0B00 0330 to 0X0B00 034E)
    274
Chapter 14 Touch Panel Interface Unit (Piu)

275
- General
  
  275
  - Block Diagrams
    276
- Scan Sequencer State Transition
  
  278
- Register Set
  
  280
  - PIUCNTREG (0X0B00 0122)
    281
  - PIUINTREG (0X0B00 0124)
    284
  - PIUSIVLREG (0X0B00 0126)
    285
  - PIUSTBLREG (0X0B00 0128)
    286
  - PIUCMDREG (0X0B00 012A)
    287
  - PIUASCNREG (0X0B00 0130)
    289
  - PIUAMSKREG (0X0B00 0132)
    291
  - PIUCIVLREG (0X0B00 013E)
    292
  - Piupbnmreg (0X0B00 02A0 to 0X0B00 02AE, 0X0B00 02BC to 0X0B00 02BE)
    293
  - Piuabnreg (0X0B00 02B0 to 0X0B00 02B6)
    294
- State Transition Flow
  
  295
- Relationships Among TPX, TPY, ADIN, and AUDIOIN Pins and States
  
  297
- Timing
  
  298
  - Touch/Release Detection Timing
    298
  - A/D Port Scan Timing
    298
- Data Loss Conditions
  
  299
Chapter 15 Audio Interface Unit (Aiu)

301
- General
  
  301
- Register Set
  
  302
  - SDMADATREG (0X0B00 0160)
    303
  - MDMADATREG (0X0B00 0162)
    304
  - DAVREF_SETUP (0X0B00 0164)
    305
  - SODATREG (0X0B00 0166)
    306
  - SCNTREG (0X0B00 0168)
    307
  - SCNVC_END (0X0B00 016E)
    308
  - MIDATREG (0X0B00 0170)
    309
  - MCNTREG (0X0B00 0172)
    310
  - DVALIDREG (0X0B00 0178)
    311
  - SEQREG (0X0B00 017A)
    312
  - INTREG (0X0B00 017C)
    313
  - MCNVC_END (0X0B00 017E)
    314
- Operation Sequence
  
  315
  - Output (Speaker)
    315
  - Input (Microphone)
    316
Chapter 16 Keyboard Interface Unit (Kiu)

317
- General
  
  317
- Functional Description
  
  317
  - Automatic Keyboard Scan Mode (Auto Scan Mode)
    318
  - Manual Keyboard Scan Mode (Manual Scan Mode)
    318
  - Key Press Detection
    318
  - Scan Operation
    319
  - Reading Scanned Data
    320
  - Interrupts and Status Reporting
    320
- Register Set
  
  321
  - Kiudatn (0X0B00 0180 to 0X0B00 018E)
    322
  - KIUSCANREP (0X0B00 0190)
    323
  - KIUSCANS (0X0B00 0192)
    324
  - KIUWKS (0X0B00 0194)
    325
  - KIUWKI (0X0B00 0196)
    326
  - KIUINT (0X0B00 0198)
    327
Chapter 17 Compactflash Controller (Ecu)

328
- General
  
  328
- Register Set Summary
  
  328
- ECU Control Registers
  
  331
  - INTSTATREG (0X0B00 08F8)
    331
  - INTMSKREG (0X0B00 08FA)
    332
  - CFG_REG_1 (0X0B00 08FE)
    333
- ECU Registers
  
  334
  - ID_REV_REG (Index: 0X00)
    334
  - IF_STAT_REG (Index: 0X01)
    335
  - PWRRSETDRV (Index: 0X02)
    336
  - ITGENCTREG (Index: 0X03)
    337
  - CDSTCHGREG (Index: 0X04)
    338
  - CRDSTATREG (Index: 0X05)
    339
  - ADWINENREG (Index: 0X06)
    340
  - IOCTRL_REG (Index: 0X07)
    341
  - Ioadslbnreg (Index: 0X08, 0X0C)
    342
  - Ioadshbnreg (Index: 0X09, 0X0D)
    342
  - Ioslbnreg (Index: 0X0A, 0X0E)
    343
  - Ioshbnreg (Index: 0X0B, 0X0F)
    343
  - Sysmemslnreg (Index: 0X10, 0X18, 0X20, 0X28, 0X30)
    344
  - Memwidn_Reg (Index: 0X11, 0X19, 0X21, 0X29, 0X31)
    344
  - Sysmemelnreg (Index: 0X12, 0X1A, 0X22, 0X2A, 0X32)
    345
  - Memseln_Reg (Index: 0X13, 0X1B, 0X23, 0X2B, 0X33)
    345
  - Memofflnreg (Index: 0X14, 0X1C, 0X24, 0X2C, 0X34)
    346
  - Memoffhnreg (Index: 0X15, 0X1D, 0X25, 0X2D, 0X35)
    346
  - DTGENCLREG (Index: 0X16)
    347
  - GLOCTRLREG (Index: 0X1E)
    348
  - VOLTSENREG (Index: 0X1F)
    348
  - VOLTSELREG (Index: 0X2F)
    349
- Memory Mapping of Compactflash Card
  
  350
- Controlling Bus When Compactflash Card Is Used
  
  352
  - Controlling Bus Size
    352
  - Controlling Wait
    352
Chapter 18 Led Control Unit (Led)

353
- General
  
  353
- Register Set
  
  353
  - LEDHTSREG (0X0B00 0240)
    354
  - LEDLTSREG (0X0B00 0242)
    355
  - LEDCNTREG (0X0B00 0248)
    356
  - LEDASTCREG (0X0B00 024A)
    357
  - LEDINTREG (0X0B00 024C)
    358
- Operation Flow
  
  359
Chapter 19 Serial Interface Unit 1 (Siu1)

360
- General
  
  360
- Clock Control Logic
  
  360
- Register Set
  
  361
  - SIURB_1 (0X0C00 0010: LCR7 = 0, Read)
    362
  - SIUTH_1 (0X0C00 0010: LCR7 = 0, Write)
    362
  - SIUDLL_1 (0X0C00 0010: LCR7 = 1)
    362
  - SIUIE_1 (0X0C00 0011: LCR7 = 0)
    363
  - SIUDLM_1 (0X0C00 0011: LCR7 = 1)
    364
  - SIUIID_1 (0X0C00 0012: Read)
    366
  - SIUFC_1 (0X0C00 0012: Write)
    368
  - SIULC_1 (0X0C00 0013)
    371
  - SIUMC_1 (0X0C00 0014)
    372
  - SIULS_1 (0X0C00 0015)
    373
  - SIUMS_1 (0X0C00 0016)
    375
  - SIUSC_1 (0X0C00 0017)
    376
  - SIURESET_1 (0X0C00 0019)
    376
  - SIUACTMSK_1 (0X0C00 001C)
    377
  - SIUACTTMR_1 (0X0C00 001E)
    378
Chapter 20 Serial Interface Unit 2 (Siu2)

379
- General
  
  379
- Clock Control Logic
  
  379
- Register Set
  
  380
  - SIURB_2 (0X0C00 0000: LCR7 = 0, Read)
    381
  - SIUTH_2 (0X0C00 0000: LCR7 = 0, Write)
    381
  - SIUDLL_2 (0X0C00 0000: LCR7 = 1)
    381
  - SIUIE_2 (0X0C00 0001: LCR7 = 0)
    382
  - SIUDLM_2 (0X0C00 0001: LCR7 = 1)
    383
  - SIUIID_2 (0X0C00 0002: Read)
    385
  - SIUFC_2 (0X0C00 0002: Write)
    387
  - SIULC_2 (0X0C00 0003)
    390
  - SIUMC_2 (0X0C00 0004)
    391
  - SIULS_2 (0X0C00 0005)
    392
  - SIUMS_2 (0X0C00 0006)
    394
  - SIUSC_2 (0X0C00 0007)
    395
  - SIUIRSEL_2 (0X0C00 0008)
    395
  - SIURESET_2 (0X0C00 0009)
    396
  - SIUCSEL_2 (0X0C00 000A)
    396
  - SIUACTMSK_2 (0X0C00 000C)
    397
  - SIUACTTMR_2 (0X0C00 000E)
    398
Chapter 21 Lcd Controller

399
- Overview
  
  399
  - LCD Interface
    399
- LCD Module Features
  
  400
- LCD Controller Specification
  
  402
  - Panel Configuration and Interface
    402
  - Controller Clocks
    405
  - Palette
    406
  - Frame Buffer Memory and FIFO
    406
  - Panel Power ON/OFF Sequence
    407
  - Operation of LCD Controller
    408
- Register Set
  
  413
  - HRTOTALREG (0X0A00 0400)
    414
  - HRVISIBREG (0X0A00 0402)
    414
  - LDCLKSTREG (0X0A00 0404)
    415
  - LDCLKENDREG (0X0A00 0406)
    415
  - VRTOTALREG (0X0A00 0408)
    416
  - VRVISIBREG (0X0A00 040A)
    416
  - FVSTARTREG (0X0A00 040C)
    417
  - FVENDREG (0X0A00 040E)
    417
  - LCDCTRLREG (0X0A00 0410)
    418
  - LCDINRQREG (0X0A00 0412)
    419
  - LCDCFGREG0 (0X0A00 0414)
    420
  - LCDCFGREG1 (0X0A00 0416)
    421
  - FBSTADREG1 (0X0A00 0418)
    422
  - FBSTADREG2 (0X0A00 041A)
    422
  - FBENDADREG1 (0X0A00 0420)
    423
  - FBENDADREG2 (0X0A00 0422)
    423
  - FHSTARTREG (0X0A00 0424)
    424
  - FHENDREG (0X0A00 0426)
    424
  - PWRCONREG1 (0X0A00 0430)
    425
  - PWRCONREG2 (0X0A00 0432)
    426
  - LCDIMSKREG (0X0A00 0434)
    427
  - CPINDCTREG (0X0A00 047E)
    428
  - CPALDATREG (0X0A0 0480)
    429
Chapter 22 Pll Passive Components

430
Chapter 23 Coprocessor 0 Hazards

431
Appendix A Restrictions on V

436
- RSTSW# During Haltimer Operation
  
  436
- RSTSW# in Hibernate Mode
  
  437
Appendix B Index

439

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Telephone

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NEC VR4181 mPD30181 Manuals

NEC VR4181 mPD30181 User Manual (444 pages)

Table of Contents

Chapter 1 Introduction

Features

Ordering Information

R 4181 Key Features

R 4110 CPU Core

Clock Interface

Chapter 2 Pin Functions

Pin Configuration

Pin Function Description

Pin Status in Specific Status

Recommended Connection of Unused Pins and I/O Circuit Types

Pin I/O Circuits

Chapter 3 Cp0 Registers

Coprocessor 0 (CP0)

Details of CP0 Registers

Chapter 4 Memory Management System

Overview

Physical Address Space

Chapter 5 Initialization Interface

Reset Function

Power-On Sequence

Reset of CPU Core

Notes on Initialization

Chapter 6 Bus Control

MBA Host Bridge

Bus Control Registers

ROM Interface

DRAM Interface

Memory Controller Register Set

ISA Bridge Register Set

ISA Bridge

Chapter 7 Dma Control Unit (Dcu)

General

DCU Registers

Chapter 8 Clocked Serial Interface Unit (Csi)

Overview

Operation of CSI

CSI Registers

Chapter 9 Interrupt Control Unit (Icu)

Overview

Register Set

Chapter 10 Power Management Unit (Pmu)

General

R 4181 Power Mode

Reset Control

Shutdown Control

Power-On Control

DRAM Interface Control

Register Set

Chapter 11 Realtime Clock Unit (Rtc)

General

Register Set

Chapter 12 Deadman's Switch Unit (Dsu)

General

Register Set

Register Setting Flow

Chapter 13 General Purpose I/O Unit (Giu)

Overview

Alternate Functions Overview

Register Set

Chapter 14 Touch Panel Interface Unit (Piu)

General

Scan Sequencer State Transition

Register Set

State Transition Flow

Relationships Among TPX, TPY, ADIN, and AUDIOIN Pins and States

Timing

Data Loss Conditions

Chapter 15 Audio Interface Unit (Aiu)

General

Register Set

Operation Sequence

Chapter 16 Keyboard Interface Unit (Kiu)

General

Functional Description

Register Set

Chapter 17 Compactflash Controller (Ecu)