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Manuals and User Guides for Motorola MC9S12GC32. We have
1
Motorola MC9S12GC32 manual available for free PDF download: User Manual
Motorola MC9S12GC32 User Manual (136 pages)
Motorola Network Device User Guide
Brand:
Motorola
| Category:
Network Hardware
| Size: 2.14 MB
Table of Contents
Revision History
2
Table of Contents
3
Table 0-2 MC9S12C-Family Package Option Summary
15
Table 0-1 List of MC9S12C and MC9S12GC Family Members
15
Figure 0-1 Order Part Number Coding
16
Table 0-3 MC9S12C-Family Part Number Coding
16
Table 0-4 MC9S12GC-Family Part Number Coding
19
Table 0-5 Document References
21
Section 1 Introduction
23
Overview
23
Features
23
Modes of Operation
25
Block Diagram
27
Figure 1-1 MC9S12C-Family Block Diagram
27
Device Memory Map
28
Table 1-1 Device Register Map Overview
28
Figure 1-2 MC9S12C128 and MC9S12GC128 User Configurable Memory Map
29
Figure 1-3 MC9S12C96 User Configurable Memory Map
30
Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map
31
Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map
32
Detailed Register Map
33
Figure 1-6 MC9S12GC16 User Configurable Memory Map
33
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
46
Part ID Assignments
50
Section 2 Signal Description
52
Device Pinout
52
Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family
52
Figure 2-2 Pin Assignments in 52 LQFP for MC9S12C-Family
53
Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family
54
Signal Properties Summary
55
Pin Initialization for 48 & 52 Pin LQFP Bond-Out Versions
56
Detailed Signal Descriptions
57
EXTAL, XTAL - Oscillator Pins
57
RESET - External Reset Pin
57
TEST / VPP - Test Pin
57
XFC - PLL Loop Filter Pin
57
Figure 2-4 PLL Loop Filter Connections
57
BKGD / TAGHI / MODC - Background Debug, Tag High & Mode Pin
58
PA[7:0] / ADDR[15:8] / DATA[15:8] - Port a I/O Pins
58
PB[7:0] / ADDR[7:0] / DATA[7:0] - Port B I/O Pins
58
PE7 / NOACC / XCLKS - Port E I/O Pin 7
58
Figure 2-5 Colpitts Oscillator Connections (PE7=1)
59
Figure 2-6 Pierce Oscillator Connections (PE7=0)
59
Figure 2-7 External Clock Connections (PE7=0)
59
PE6 / MODB / IPIPE1 - Port E I/O Pin 6
60
PE5 / MODA / IPIPE0 - Port E I/O Pin 5
60
PE4 / ECLK- Port E I/O Pin [4] / E-Clock Output
60
PE3 / LSTRB - Port E I/O Pin [3] / Low-Byte Strobe (LSTRB)
60
PE2 / R/W - Port E I/O Pin [2] / Read/Write
60
PE1 / IRQ - Port E Input Pin [1] / Maskable Interrupt Pin
61
PE0 / XIRQ - Port E Input Pin [0] / Non Maskable Interrupt Pin
61
PAD[7:0] / AN[7:0] - Port AD I/O Pins [7:0]
61
PP[7] / KWP[7] - Port P I/O Pin [7]
61
PP[6] / KWP[6]/ROMCTL - Port P I/O Pin [6]
61
PP[5:0] / KWP[5:0] / PW[5:0] - Port P I/O Pins [5:0]
62
PJ[7:6] / KWJ[7:6] - Port J I/O Pins [7:6]
62
PM5 / SCK - Port M I/O Pin 5
62
PM4 / MOSI - Port M I/O Pin 4
62
PM3 / SS - Port M I/O Pin 3
62
PM2 / MISO - Port M I/O Pin 2
62
PM1 / TXCAN - Port M I/O Pin 1
62
PM0 / RXCAN - Port M I/O Pin 0
62
PS[3:2] - Port S I/O Pins [3:2]
63
PS1 / TXD - Port S I/O Pin 1
63
PS0 / RXD - Port S I/O Pin 0
63
PS0 / RXD — Port I/O Pin
63
PPT[7:5] / IOC[7:5] - Port T I/O Pins [7:5]
63
PT[4:0] / IOC[4:0] / PW[4:0]- Port T I/O Pins [4:0]
63
Power Supply Pins
63
VDDX,VSSX - Power & Ground Pins for I/O Drivers
63
VDDR, VSSR - Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
63
VDD1, VDD2, VSS1, VSS2 - Internal Logic Power Pins
63
VDDA, VSSA - Power Supply Pins for ATD and VREG
64
VRH, VRL - ATD Reference Voltage Input Pins
64
VDDPLL, VSSPLL - Power Supply Pins for PLL
64
Section 3 System Clock Description
64
Section 4 Modes of Operation
65
Overview
65
Chip Configuration Summary
65
Figure 3-1 Clock Connections
65
Security
66
Securing the Microcontroller
67
Operation of the Secured Microcontroller
67
Unsecuring the Microcontroller
67
Low Power Modes
67
Stop
68
Pseudo Stop
68
Wait
68
Run
68
Section 5 Resets and Interrupts
68
Overview
68
Vectors
68
Vector Table
68
Resets
69
Reset Summary Table
70
Effects of Reset
70
Section 6 HCS12 Core Block Description
70
Device-Specific Information
70
Ppage
70
BDM Alternate Clock
71
Extended Address Range Emulation Implications
71
Section 7 Voltage Regulator (VREG) Block Description
72
Device-Specific Information
72
Vregen
72
Vdd1, Vdd2, Vss1, Vss2
72
Section 8 Recommended Printed Circuit Board Layout
72
Figure 8-1 Recommended PCB Layout (48 LQFP)
74
Figure 8-2 Recommended PCB Layout (52 LQFP)
75
Figure 8-3 Recommended PCB Layout (80 QFP)
76
Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator
77
Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator
78
Section 9 Clock Reset Generator (CRG) Block Description
79
Device-Specific Information
79
Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator
79
Xclks
80
Section 10 Oscillator (OSC) Block Description
80
Section 11 Timer (TIM) Block Description
80
Section 12 Analog to Digital Converter (ATD) Block Description
80
Device-Specific Information
80
VRL (Voltage Reference Low)
80
Section 13 Serial Communications Interface (SCI) Block Description
80
Section 14 Serial Peripheral Interface (SPI) Block Description
80
Section 16 RAM Block Description
81
Section 17 Pulse Width Modulator (PWM) Block Description
81
Section 18 MSCAN Block Description
81
Section 19 Port Integration Module (PIM) Block Description
81
Appendix A Electrical Characteristics
83
General
83
Parameter Classification
83
Power Supply
83
A.1 General
83
A.1.1 Parameter Classification
83
A.1.2 Power Supply
83
Pins
84
Current Injection
84
A.1.3 Pins
84
A.1.4 Current Injection
84
Absolute Maximum Ratings
85
ESD Protection and Latch-Up Immunity
86
Operating Conditions
86
A.1.7 Operating Conditions
86
Power Dissipation and Thermal Characteristics
87
I/O Characteristics
89
A.1.9 I/O Characteristics
89
Supply Currents
92
A.1.10 Supply Currents
92
Appendix B Electrical Specifications
95
Voltage Regulator Operating Conditions
95
Chip Power-Up and LVI/LVR Graphical Explanation
96
Output Loads
96
Resistive Loads
96
B.3 Output Loads
96
B.3.1 Resistive Loads
96
Figure B-1 Voltage Regulator - Chip Power-Up and Voltage Drops (Not Scaled)
96
Capacitive Loads
97
B.3.2 Capacitive Loads
97
ATD Characteristics
99
B.4 ATD Characteristics
99
ATD Operating Characteristics in 5V Range
99
ATD Operating Characteristics in 3.3V Range
99
Factors Influencing Accuracy
100
ATD Accuracy (5V Range)
102
ATD Accuracy (3.3V Range)
102
Figure B-2 ATD Accuracy Definitions
104
NVM, Flash and EEPROM
105
NVM Timing
105
B.5.1 NVM Timing
105
NVM Reliability
107
B.5.2 NVM Reliability
107
Reset, Oscillator and PLL
109
Startup
109
B.6.1 Startup
109
Oscillator
110
B.6.2 Oscillator
110
Phase Locked Loop
111
Figure B-3 Basic PLL Functional Diagram
112
Figure B-4 Jitter Definitions
114
Figure B-5 Maximum Bus Clock Jitter Approximation
114
Mscan
117
B.7 Mscan
117
Spi
119
Appendix C Electrical Specifications
119
Master Mode
119
Figure C-1 SPI Master Timing (CPHA=0)
119
C.1 Master Mode
119
Figure C-2 SPI Master Timing (CPHA=1)
120
Slave Mode
121
Figure C-3 SPI Slave Timing (CPHA=0)
121
C.2 Slave Mode
121
Figure C-4 SPI Slave Timing (CPHA=1)
122
External Bus Timing
123
General Muxed Bus Timing
123
Figure C-5 General External Bus Timing
123
Appendix D Package Information
127
General
127
D.1 General
127
80-Pin QFP Package
128
Figure D-1 80-Pin QFP Mechanical Dimensions (Case No. 841B)
128
52-Pin LQFP Package
129
Figure D-2 52-Pin LQFP Mechanical Dimensions (Case No. 848D-03)
129
48-Pin LQFP Package
130
Appendix E Emulation Information
131
General
131
E.1 General
131
Pk[2:0] / Xaddr[16:14]
132
E.1.1 Pk[2:0] / Xaddr[16:14]
132
112-Pin LQFP Package
133
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