Pioneer MD-P100 Service Manual page 33

Pin No. Pin Name
45 EFMO
46 RAOF
47 MVCI
48 TEST2
49 DIPD
50 DVSS1
51 DICV
52 DIFI
53 DIFO
54 AVDD1
55 ASYO
56 ASYI
57 BIAS
58 RFI
59 AVSS1
60 CLTV
61 PCO
62 FILI
63 FILO
64 PEAK
65 BOTM
66 ABCD
67 FE
68 AUX1
69 VC
70 ADIO
71 TEST3
72 AVDD2
73 ADRT
74 ADRB
75 AVSS2
76 SE
77 TE
78 AUX2
79 DCHG
80 APC
81 TEST1
82 ADFG
83 TS25
84 LDDR
85 TRDR
86 TFDR
87 FFDR
88 DVDD1
89 FRDR
90 FS4
91 SRDR
92 SFDR
93 SPRD
94 SPFD
95 DCLO
I/O Function and Operation
O FM signal output (Whcn recoding) Not used this set (OPEN)
O Overflow detection signal output of the internal RAM (Decoder monitor out)
RAOF is signal generated when the 32k RAM exceeds the ±4F jitter margin
Not used this set (OPEN)
I Oscillation input for PLL of the digital in Not used this set (Fixed at "L")
I Test terminal input (Fixed at "L")
O Phase comparator output for PLL of the digital in
When the internal VCO:Frequency;Low→"H"
When the external VCO:Frequency;Low→"L" Not used this set (OPEN)
Ground terminal (Digital system)
I Control voltage input terminal of the internal VCO for digital in PLL
I Filter input terminal of the internal VCO for digital in PLL
Not used this set (Fixed at "L")
O Filter output terminal of the internal VCO for digital in PLL
Not used this set (OPEN)
Power supply terminal (+3.3V) (Analog system)
O Playback EFM full-swing output (L=VSS,H=VDD)
I Playback EFM asymmetry comparate voltage input terminal
I Playback EFM asymmetry circuit constant current input terminal
I Playback EFM RF signal input from CXA1981AR (IC100)
Ground terminal (Analog system)
I VCO control voltage input terminal of the PLL for decoder PLL master clock
O Phase comparator output terminal of the PLL for decoder PLL master clock
I Filter input terminal of the PLL for decoder PLL master clock
O Filter output terminal of the PLL for decoder PLL master clock
I Light amount peak hold signal input from CXA1981AR (IC100)
I Light amount bottom hold signal input from CXA1981AR (IC100)
I Light amount signal input from CXA1981AR (IC100)
I Focus error signal input from CXA1981AR (IC100)
I Sub signal input from CXA1981AR (IC100)
I Center point voltage (1/2 VCC) input from CXA1981AR (IC100)
O Monitor output of the A/D converter input signal Not used this set (OPEN)
I Test input terminal (Fixed at "L")
Power supply terminal (+3.3V) (Analog system)
I A/D converter action limits (upper side) voltage input (Fixed at "H")
I A/D converter action limits (lower side) voltage input (Fixed at "L")
Ground terminal (Analog system)
I Sled error signal input from CXA1981AR (IC100)
I Tracking error signal input from CXA1981AR (IC100)
I Sub signal input terminal from CXA1981AR (IC100)
I Connected to the Ground
I Input terminal for the laser APC Not used this set (Fixed at "L")
I Test input terminal (Fixed at "L")
I ADIP double turned FM signal input from CXA1981AR (IC100)
(22.05kHz ±1kHz) (TTL schmitt input)
I Test input terminal (Fixed at "L")
O Laser APC signal output to CXA1981AR (IC100)
O Tracking servo drive signal output (-)
O Tracking servo drive signal output (+)
O Focus servo drive signal output (+)
Power supply terminal (+3.3V) (Digital system)
O Focus servo drive signal output (-)
O 176.4kHz clock signal output (MCLK system) Not used this set (OPEN)
O Sled servo drive signal output (+)
O Sled servo drive signal output (-)
O Spindle servo drive signal output (+)
O Spindle servo drive signal output (-)
O Not used (OPEN)
MD-P100
33