Table Of Contents - HP 27130A Technical Reference Manual

Eight -channel mul tiplexer (mux)
Table of Contents

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CONTENTS
Section I
Page
PhY5icai De5cription .•.•..•••.••.••••••.•••••.••.•••••.•••...••.. 1-1
Functional Description ....• ·.;, •.•..•........•..•..............•... 1-1
Equipment Supplied ............................................... 1-3
Identification ................................................... 1-3
~
............................................... 1-3
Printed Circuit Card ....••...•.•.••••....•..••...•.•.••.•.•••.. 1-3
fw1a.nua15 ..••.•.•••••...••••••.••.••••••.••••••••••••••••.••••••• 1-4
Specifications ................................................... 1-4
Section II
Page
Determining Current Requirements .•.•.•...••••.••.•••..••••••.•... 2-1
Firmware (EPROM> In5tallation ....•••.•.•.••••.•.••..•.••..••.•... 2-1
5 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
2 - 3
Memory Configuration Jumper •.•...•...•...•...........••........
2-3
Signature AnalY5i5 Jumper ..•.......•••..•.•.........•.•..•.••..
2-3
liD
Channel Interface ....•...•..•.•.••..•........•........•......
2-5
Peripheral Device Interface ..•.••.••••..•.•......................
2-5
In5talling the MUX .•....•••..•.•......•...•.•....•...•..•.•..•.. 2-12
Checkout ........................................................ 2-13
Reshipment ......................
2-14
Section III
Page
Functional de5cription ......•.•••..••.•...............•......•... 3-1
5 . • . • • • . . • • • • • • • • • • • • • • • • • • • • • • . • • • • • • • . • • • . • • • • • • •
3- 3
Memory Addre55 Space ....•.......••.••••••••.••...........•.•... 3-3
110 Address Space ...............
e • • • • • • • • • • • e . • • • • • • • • • • • • • • • • • •
3-6
Z-80B
Microproc·e550r CPU ...............•....................... 3-6
Z-80 510/2
(Serial
liD
Controller> .•.•.••••..•..•.....•.••.•... 3-6
CTC (Counter Timer Circuit .....•••.•
~
•.•.••.•.•.•..•...••.••.. 3-19
Interfac·ing to the BIC .••..•.....•••.•.•••..••••.•.•..••.•••.. 3-19
Memory Interface Circuit (MIC) .•••.•.•.•.•..•••.•..•..•.••.•.. 3-24
Regi 5 ter 0 - MI C Conf igurat ion •...•....•......•..•....•..•.. 3-24
Regi5ter 1 - DMA B Upper Byte of Memory Addre55 ....••....•.. 3-24
Regi5ter 2 - DMA Lower Byte of Memory Addre55 .......•.••.•.. 3-24
Regi5ter 3 - DMA B Configuration .•.•.•.••.••.....•..•....•.. 3-25
Regi5ter 4 - Lower Byte of Tran5fer Byte Count •.....•.••.••. 3-25
Regi 5ter
5 -
DMA B
110
Port Addre55 •.•.•.........•..•.•..•..
3-25
Regi5ter 6 - DMA A Upper Byte of Memory Addre55 .....•..•.•.. 3-25
Regi5ter 7 - DMA A Lower Byte of Memory Addre55 ............. 3-25
Regi5ter 8 - DMA A Configuration .......•..............•...•. 3-26
iii

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