Sony DP-IF8000 Service Manual page 6

DP-IF8000
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3 7 63 1515 0
LRCK
BCK
LPOUT2
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
32 kHz are also used.
LRCK
BCK
VPOUT2
• MAIN DSP-DIAT period
Check RCS (IC12-109pin), BCK (IC12-106), VPOUT1 (IC12-
96pin), RINFO (IC12-107pin).
Turn the power on, set in Digital Input mode, and select VIRTUAL
FRONT, or VIRTUAL 5.1 or VIRTUAL 6.1 with the OUTPUT
switch.
The view on the monitor when the input source sampling frequency
is 48 kHz is shown in Fig. 11.
The view on the monitor when the input source sampling frequency
is 44.1 kHz is shown in Fig. 12.
The view on the monitor when the input source sampling frequency
is 32 kHz is shown in Fig. 13.
RCS
BCK
TE
L 13942296513
VPOU1
RINFO
Note 4: fs=48kHz
Fig 11
RCS
BCK
VPOU1
RINFO
Note 5: fs=44.1kHz
Fig 12
RCS
BCK
VPOU1
RINFO
Note 6: fs=32kHz
Fig 13
When OFF is selected with the OUTPUT key, check the DILRCK
(IC12-98pin), BCK (IC12-106pin), VPOUT1 (IC12-96pin), and the
view on the monitor should be the same as the MAIN DSP-DAC
period.
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Lch Rch
Fig 9
Fig 10
0001000 t fs=48k
0000000 t fs=44.1k
0011000 t fs=32k
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2.1.2 System Control
Note: Input a signal of some kind to DIGITAL IN 1 and LINE IN.
• MICON-DIR period
Check the DIR_XCS (IC4-37pin), SCK2 (IC4-38pin), and SDO2
(IC4-36pin).
Figure 14 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key.
DIR_XCS
SCK
(500KHZ)
SDO2
• MICON-DAC period
Check the DAC_XCS (IC5-10pin), SCKO (IC5-8pin), and SDO02
(IC5-9pin).
Figure 15 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key.
DAC_XCS
SCK 0
(500KHZ)
SDO 0
Q Q
3 6 7 1 3
• MICON-LED DRIVER period
Check the LED_XLAT (CN102-3pin), SCKO(CN102-6pin), and
SDO(CN102-7pin).
Figure 16 shows the view on the monitor after power is turned on,
at the instant of switching with each key.
LED_XLAT
SCK 0
(500KHZ)
SDO 0
• MICON-DIAT period
Check the DIAT_LAT (IC12-152pin), SCKO (IC12-151pin), SDO
(IC12-153pin).
Figure 17 shows the view on the monitor after power is turned on,
at the instant of switching with the INPUT key. The timing is shown
in detail in FIG. 18.
DIAT_LAT
SCK 0
SDO 0
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DIAT_LAT
SCK 0
(500KHZ) .
SDO 0
2 9 9 4 2 8
Address data
8 bit 8 bit + 8 bit
00010111
Fig 14
Address data
8 bit 8 bit + 8 bit
00100000
1 5 0 5 8 2 9 9 4
Fig 15
after data transfer LAT
8 bit + 8 bit
Fig 16
m
Fig 17
co
after 24bit data transfer LAT
Fig 18
9 9
2 8 9 9