Audio Processing And Digital Volume Control; Audio Amplification Speaker (+) Speaker (-) - Motorola GTX/LCS 2000 Service Manual

Audio Processing and Digital
Volume Control
Audio Amplification Speaker
(+) Speaker (-)
ACT. The state of CH ACT and SQ DET is high (logic 1) when carrier is detected,
otherwise low (logic 0).
CH ACT is routed to the µP pin 25 while SQ DET adds up with LOCK DET,
weighted by resistors R0113, R0114, and is routed to one of the µP´s ADC input
U0101-43. From the voltage weighted by the resistors the µP determines whether
SQ DET, LOCK DET or both are active.
SQ DET is used to determine all audio mute / unmute decisions except for
Conventional Scan. In this case CH ACT is a pre-indicator as it occurs slightly
faster than SQ DET.
The receiver audio signal enters the controller section from the IF IC (U5201-28)
on DET AUDIO and passes through RC filter R0203 and C0208 which filters out
IF noise. The signal is AC coupled by C0207 and enters the ASFIC via the PL IN
pin U0201-J7.
Inside the ASFIC, the signal goes through two paths in parallel, the audio path and
the PL/DPL path.
The audio path has a programmable amplifier, whose setting is based on the
channel bandwidth being received, then a LPF filter to remove any frequency
components above 3000Hz and then an HPF to strip off any sub-audible data
below 300Hz. Next, the recovered audio passes through a de-emphasis filter if it
is enabled (to compensate for Pre-emphasis which is used to reduce the effects of
FM noise). The IC then passes the audio through the 8-bit programmable
attenuator whose level is set depending on the value of the volume control. Finally
the filtered audio signal passes through an output buffer within the ASFIC. The
audio signal exits the ASFIC at RX AUDIO (U0201-J4).
The µP programs the attenuator, using the SPI BUS, based on the volume setting.
The minimum /maximum settings of the attenuator are set by codeplug
parameters.
Since sub-audible signalling is summed with voice information on transmit, it
must be separated from the voice information before processing. Any sub-audible
signalling enters the ASFIC from the IF IC at PL IN U0201-J7. Once inside it goes
through the PL/DPL path.
The signal first passes through one of 2 low pass filters, either PL low pass filter
or DPL/LST low pass filter. Either signal is then filtered and goes through a limiter
and exits the ASFIC at PL LIM (U0201-A4). At this point the signal will appear
as a square wave version of the sub-audible signal which the radio received. The
microprocessor (U0101-10) will decode the signal directly to determine if it is the
tone / code which is currently active on that mode.
The ASFIC's received audio signal output, U0201-J4, is routed through a voltage
divider formed by R0401 and R0402 to set the correct input level to the audio PA
(U0401). This is necessary because the gain of the audio PA is 46 dB, and the
ASFIC output is capable of overdriving the PA unless the maximum volume is
limited.
The audio then passes through C0401 which provides AC coupling and low
frequency roll-off. C0402 provides high frequency roll-off as the audio signal is
routed to pins 1 and 9 of the audio power amplifier U0401.
Theory of Operation 7-19