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Model 5304A
Theory of Operation
the 5300A m a i n f r a m e at A1 Pi(16) is routed through
U12C as the F2 signal to control the time base,
which clocks the opening and closing of the main
gate.
9D-4-15. The positive-going edge of a negative pulse
from U17E is the MAX TIME signal.
The MAX
TIME signal a t A1 Pi(17) triggers a display cycle in
the 5300A mainframe.
This negative-going pulse
can be generated from one of two sources.
One
of the sources is the positive-going edge of the
MGFF line at A1P1(12) which indicates the closing
of the 5300A main gate.
This signal is inverted
through U17D and differentiated l>y CI4 and R69.
CR18 is a clamping diode to
shorten
the
dif-
ferentiation
recovery time.
The negative pulse
of the differentiated waveform, gates U16A " o n "
and the narrow
positive-going pulse is inverted
through U17E as the MAX TIME signal.
9D-4-16. The TIME BASE O U T signal at AlPl(18)
comes from the 5300A m a i n f r a m e and is buffered
by Q18 then gated through U14C, U1HA, and inverted
through U17E as the MAX TIME signal.
9D-4-17.
The positive-going edge of the negative
pulse at A1PK17), indicates the display cycle h a s
been triggered.
9D-4-18. PERIOD AVG A MODE. In period a v e r a g e
mode the "function" switch S2 enables U l A , U6D,
U12C, and U14A.
The Channel A signal is routed
through "Channel A Slope Selection" and " C h a n n e l
A Switch" at U18B(6).
The signal is then gated
through U16C and is available at AlPl(21) a s the 1
MHz TIME BASE. The CLOCK signal at A1P1(16)
is gated through U12A, U16B a s the F l signal to
be counted.
9D4-19. Flip-flop U4A prevents very narrow pulses
from triggering the time base but not the main
gate. The first Channel A pulse after the I N H I B I T
signal goes high at the end of the display cycle
"clocks" U4A(5) to a high state and enables U16C.
The next positive-going edge of the Channel A signal
is gated through U16C a s the 1 MHz T I M E BASE
INPUT signal.
The main gate is then closed by
one of two events. The first event is: The 9 signal
line from 5300A, U3 COUNTER, goes low, and
enables the main gate in the 5300A, U5 CONTROL,
to close on the next LOG pulse.
When the 9 line
goes low it indicates t h a t the display is 9% full.
The main gate closes at the end of the next decade-
multiple of the input signal to prevent overflow. The
second event is:
The TIME BASE O U T signal
(A1P1(18)) from the 5300A, U4 TIME BASE goes
low indicating the I0
a
periods have been counted.
The main gate closes because no more counts can
be stored in the 5304A exponent counter U8A and U8B.
The exponent counter counts the number of decade-
transitions of the
input
signal
t h a t
have
been
counted (1, 10, 100, 1000 input transitions or ex-
ponent counts of 1, 2, 3, 4).
9D-4-20.
The LOG O U T P U T signal (generated by
5300A, U4 TIME BASE) is active in Frequency and
Period Average Modes and provides pulses to open
and close the main gate.
Following a display cycle
and reset, the first LOG pulse opens the main gate
and a following LOG pulse will close the gate only
after a 9 or MAX TIME low signal enables the
closing of the main gate flip-flop.
9D-4-21.
O P E N / C L O S E A MODE.
In open/close
mode, with the "function" switch S2 in O P E N /
CLOSE position the main gate is opened and closed
by successive actuations of pushbutton switch SI.
The Channel A input signal is gated through "Slope
Selection" switch U19C, U20B, and U20C to " C h a n -
nel A Switch" U18A and U18B.
9D-4-22.
T h e Channel A input signal
is gated
through U12B, U16B to be counted.
U4B "clocks"
on successive actuations of the SI O P E N / C L O S E
switch.
When U8B(9) output is low the 5300A
main
gate
is
opened
(through
U19B).
When
U4B(8) output is low the 5300A main gate is closed
(through U14D and U22A).
When the "Function"
switch S2 is in a position other t h a n O P E N / C L O S E ,
the U4B Preset and Clear lines (U4B pins 10 and 13
respectively) are set through U10A and B, so that
IJ4B, Q and Q output (U4 pins 9 and 8) are high.
9D-4-23.
TIME INTERVAL A-B MODE.
In the
time interval mode, the "function" switch S2 may
be set to a n y one of six time-interval positions
(.1 /Jsec to 10 msec). The 5300A main gate is opened
by a Channel A transition and closed by a Channel B
transition.
Switch A2S1 enables the input signals
to
be taken
from separate
sources or
from
a
common source.
9D-4-24.
The Channel
A signal, after passing
through
A2
Attenuator
Assembly,
is
processed
through Channel A amplifier, Q2 Q4 and differntial
amplifiers Q6, Q8, and U24B.
T h e U24B output is
shaped
through
U24A Schmitt-Trigger
and
sent
through an ECL-to-TTL level-shifter (U21B, Q21)
to the Channel A Slope Selection circuits (U19C,
U20C, U20B).
9D-4-25. The output from U20B(4) is gated through
Channel A switch, comprised of U18A and B.
The
Channel A signal "clocks" U15B which is gated
through U9C, U19B, and opens the 5300A main gate.
During the gate-open time, the TIME BASE O U T
9D-4-2
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