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DESCRIPTION
The µ PD78F4225Y is a product in the µ PD784225Y subseries in the 78K/IV series.
The µ PD78F4225Y has a flash memory in the place of the internal ROM of the µ PD784225Y. Data can be written
to or erased from the flash memory of the µ PD78F4225F with the microcontroller mounted on a printed wiring board.
The µ PD78F4225Y is based on the µ PD78F4225 with an I
applications in audio visual.
The functions are explained in detail in the following user's manuals. Be sure to read this manual when
designing your system.
FEATURES
2
• I
C bus serial interface supporting multi task
• Pin-compatible with mask ROM model (except V
• Flash memory: 128K bytes
• Internal RAM : 4352 bytes
• Same operating voltage as mask ROM model: V
ORDERING INFORMATION
Part Number
µ PD78F4225YGC-8BT
µ PD78F4225YGK-BE9
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. U12377EJ1V0PM00 (1st edition)
Date Published May 1997 N
Printed in Japan
PRELIMINARY PRODUCT INFORMATION
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
µ PD784225, 784225Y Subseries User's Manual - Hardware : Planned
78K/IV Series User's Manual - Instruction
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
MOS INTEGRATED CIRCUIT
µ PD78F4225Y
2
C bus control function appended, and is ideal for
pin)
PP
= 1.8 to 5.5 V
DD
Package
: U10905E
©
1997
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Table of Contents
Related Manuals for NEC uPD78F4225Y
Summary of Contents for NEC uPD78F4225Y
- Page 1 The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production.
- Page 2 µ PD78F4225Y 78K/IV Series Product Development : Under mass production : Under development C bus compatible model µ PD784038Y µ PD784038 Enhanced internal memory capacity, µ pin-compatible with PD784026 µ PD784026 Multi-master I C bus Multi-master I C bus compatible model compatible model Enhaced A/D, 16-bit timer, power management...
- Page 3 µ PD78F4225Y FUNCTIONS Item Function Number of basic instructions (mnemonics) 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) General-purpose register Minimum instruction execution • 160 ns/320 ns/640 ns/1280 ns/2560 ns (main system clock: f = 12.5 MHz) •...
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Page 4: Table Of Contents
µ PD78F4225Y CONTENTS DIFFERENCES AMONG MODELS IN µ PD784225Y SUBSERIES ..........5 PIN CONFIGURATION (Top View) ....................6 BLOCK DIAGRAM ......................... 8 PIN FUNCTION ..........................9 Port Pins ..............................9 Pins Other Than Port Pins ........................11 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ... 13 INTERNAL MEMORY SIZE SELECT REGISTER (IMS) .............. -
Page 5: Differences Among Models In Μ Pd784225Y Subseries
µ PD78F4225Y 1. DIFFERENCES AMONG MODELS IN µ PD784225Y SUBSERIES The only difference among the µ PD784224Y and 784225Y lies in the internal memory capacity. The µ PD78P4225Y is provided with a 128-KB flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. -
Page 6: Pin Configuration (Top View)
µ PD78F4225Y 2. PIN CONFIGURATION (Top View) • 80-pin plastic QFP (14 × 14 mm) µ PD78F4225YGC-8BT • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µ PD78F4225YGK-BE9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P15/ANI5 RESET P16/ANI6... - Page 7 µ PD78F4225Y A8-A19 : Address Bus P130, P131 : Port13 AD0-AD7 : Address/Data Bus : Programmable Clock ANI0-ANI7 : Analog Input : Read Strobe ANO0, ANO1 : Analog Output RESET : Reset ASCK1, ASCK2 : Asynchronous Serial Clock RTP0-RTP7 : Real-time Output Port ASTB : Address Strobe RxD1, RxD2...
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Page 8: Block Diagram
µ PD78F4225Y 3. BLOCK DIAGRAM RxD1/SI1 INTP2/NMI PROGRAMMABLE UART/IOE1 TxD1/SO1 INTERRUPT INTP0, INTP1, BAUD-RATE ASCK1/SCK1 CONTROLLER INTP3-INTP6 GENERATOR RxD2/SI2 UART/IOE2 TI00 TxD2/SO2 TIMER/COUNTER BAUD-RATE TI01 (16 BITS) ASCK2/SCK2 GENERATOR SI0/SDA0 CLOCKED TIMER/COUNTER1 SERIAL (8 BITS) INTERFACE SCK0/SCL0 AD0-AD7 TIMER/COUNTER2 (8 BITS) A8-A15 A16-A19 TIMER/COUNTER5... -
Page 9: Pin Function
µ PD78F4225Y 4. PIN FUNCTION 4.1 Port Pins (1/2) Pin Name Alternate Function Function INTP0 Port 0 (P0): • 6-bit I/O port INTP1 • Can be set in input or output mode bit-wise. INTP2/NMI • Pins set in input mode can be connected to internal pull-up INTP3 resistors by software bit-wise. - Page 10 µ PD78F4225Y 4.1 Port Pins (2/2) Pin Name Alternate Function Function Port 6 (P6): • 8-bit I/O port • Can be set in input or output mode bit-wise. • All pins set in input mode can be connected to internal pull-up resistors by software.
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Page 11: Pins Other Than Port Pins
µ PD78F4225Y 4.2 Pins Other Than Port Pins (1/2) Pin Name Alternate Function Function TI00 Input External count clock input to 16-bit timer register TI01 Capture trigger signal input to capture/compare register 00 External count clock input to 8-bit timer register 1 External count clock input to 8-bit timer register 2 Output 16-bit timer output (shared by 14-bit PWM output) - Page 12 µ PD78F4225Y 4.2 Pins Other Than Port Pins (2/2) Pin Name Alternate Function Function WAIT Input To insert wait state(s) when external memory is accessed ASTB Output Strobe output to externally latch address information output to ports 4 through 6 to access external memory Output External access status output RESET...
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Page 13: I/O Circuit Type Of Respective Pins And Recommended Connections Of Unused Pins
µ PD78F4225Y 4.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins Table 4-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection of unused pins. For the circuit diagram of each type of I/O circuit, refer to Figure 4-1. Table 4-1. - Page 14 µ PD78F4225Y Table 4-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2) Pin Name I/O Circuit Type Recommended Connections of Unused Pins RESET Input — Connected to V — Open — Connected to V REF1 Connected to V TEST/V Directly connected to V...
- Page 15 µ PD78F4225Y Figure 4-1. Types of Pin I/O Circuits Type 2 Type 10-B pullup P-ch enable data P-ch IN/OUT Schmitt trigger input with hysteresis characteristics open drain N-ch output disable Type 12-C Type 5-H pullup pullup P-ch P-ch enable enable data P-ch IN/OUT...
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Page 16: Internal Memory Size Select Register (Ims)
µ PD78F4225Y 5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS) The IMS is a register that prevents by software a part of the internal memory from being used. By using this register, the memory of the µ PD78F4225Y can be mapped in the same manner as a mask ROM model with different internal memory (ROM and RAM) capacity. -
Page 17: Flash Memory Programming
µ PD78F4225Y 6. PROGRAMMING FLASH MEMORY The flash memory can be written with the µ PD78F4225Y mounted on the target board (on-board). To do so, connect a dedicated flash writer (Flashpro II) to the host machine and target system. Remark Flashpro II is a product of Naito Densei Machida Mfg. Co., Ltd. 6.1 Selecting Communication Mode To write the flash memory, use Flashpro II and serial communication. -
Page 18: Flash Memory Programming Function
µ PD78F4225Y 6.2 Flash Memory Programming Function The flash memory is written by transferring or receiving commands and data in a selected communication mode. The major functions of flush memory programming are listed in Table 6-2. Table 6-2. Major Functions of Flash Memory Programming Function Description Batch erasure... - Page 19 µ PD78F4225Y Figure 6-3. Connection of Flashpro II in I C Bus Mode µ Flashpro II PD78F4225Y Note RESET RESET SCL0 SDA0 Note n = 1, 2 Figure 6-4. Connection of Flashpro II in UART Mode (When Using UART1) µ Flashpro II PD78F4225Y Note...
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Page 20: Package Drawings
µ PD78F4225Y 7. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×14) detail of lead end NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.13 mm (0.005 inch) of 17.20±0.20 0.677±0.008 its true position (T.P.) at maximum material condition. 0.551 +0.009 +0.009 14.00±0.20 –0.008... - Page 21 µ PD78F4225Y 80 PIN PLASTIC TQFP (FINE PITCH) ( detail of lead end NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.10 mm (0.004 inch) of 0.551 +0.009 14.0±0.2 –0.008 its true position (T.P.) at maximum material condition. 0.472 +0.009 12.0±0.2 –0.008...
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Page 22: Appendix A. Development Tools
µ PD78F4225Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for supporting development of a system using the µ PD78F4225Y. Language processor software Note 1 RA78K4 Assembler package common to 78K/IV series Note 1 CC78K4 C compiler package common to 78K/IV series Note 1 CC78K4-L C compiler library source file common to 78K/IV series... - Page 23 µ PD78F4225Y Notes 1. • PC-9800 series (MS-DOS ) base • IBM PC/AT and compatible machine (PC DOS , Windows , MS-DOS, IBM DOS ) base • HP9000 series 700 (HP-UX ) base • SPARCstation (SunOS ) base • NEWS (NEWS-OS ) base 2.
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Page 24: Appendix B. Related Documents
µ PD78F4225Y APPENDIX B. RELATED DOCUMENTS Documents related to device Document Name Document No. Japanese English µ PD784224Y, 784225Y Preliminary Product Information U12376J Planned µ PD78F4225Y Preliminary Product Information U11824J This document µ PD784225, 784225Y Subseries User’s Manual - Hardware Planned Planned µ... - Page 25 Document Name Document No. Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 – Guide to Quality Assurance for Semiconductor Devices...
- Page 26 µ PD78F4225Y [MEMO]...
- Page 27 µ PD78F4225Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
- Page 28 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
- Page 29 C system, provided that the system conforms to the I C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corp. MS-DOS and Windows are trademarks of Microsoft Corp. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corp.
- Page 30 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.