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KX-B620 Series
KX-B520 Series
Capacitor C receives the transferred electric charge.
The voltage difference is outputted from source follower of Q2 and Q3. Q1 recovers the quantity of
charge in capacitor C to the constant quantity.
@sHo:
Sample and hold clock signal
This samples the continuous signal from CCD.
The timing of Vout is as follows:
ah
or
eee
valid signal level
Fig. 34
@10:
Shift register clock signal
This clock signal separately shifts the transferred data in the shift register which has two lines
of 525 bit.
The shifted data is sampled and held in¢sHo, and output as Vout.
¢1t¢:
Transferring gate clock signal
This clock signal transfers the charge in light conversion section to the shift register. The charge
in the odd element is transferred to the odd shift register. The charge in the even element is
transferred to the even element. One period of transferring gate clock equals the charging time
of the CCD.
—
Photo
array
¢ ozs
bit
use
: bit
)
CONTROL
BOARD
CCD
BOARD
Fig. 35 Circuit Diagram
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