HP 5308A Operating And Service Manual page 28

Model 5308A
Theory of Operation
to the 4-to-10 line decoder, U25, where the 3 lines are
decoded to drive the decimal point lines.
9H-4-15. When operating in the AUTO mode, the
AUTO/X1 line from J1 activates the Exponent
Counter/Latch, U28. This is a tri-state device that is
normally in its high-impedance (off) state; however, in
AUTO, the OD (output disable) inputs are Low, and the
device is free to count LOG pulses. Since the log pulses
occur for each 10N accumulation of the F2 signal, they
directly represent the magnitude of the measurement
being made and can, therefore, be used to adjust the
. decimal point and annunciators as the measurement
progresses.
9H-4-16. When a measurement is in progress, the
results ofthe previous measurement are being displayed
and the exponent counter is being clocked by LOG
pulses. The output states remain fixed, however, to
maintain the proper decimal point and annunciator for
the current display. Once the measurement ends, both
inputs of U19C go Low and allow U28 to transfer its
internally stored count to the ROM.
$H-4-17. Automatic Time Base Mode
9H-4-18. When the TIME BASE switch is set to the
AUTO position, the counter provides a special
measurement feature for four modes of operation: Time
Interval Average, Frequency A, Frequency A/B, and
Period Average B. For any one of these modes, the
counter will perform a measurement within a one second
gate time. The gate time is not fixed but for the majority
of cases will vary between 0.11 s and 1.1 s.
9H-4-19. The measurement starts when the Auxiliary
Gate Flip Flop (AGFF, U17A) is clocked by the "time
zero" LOG pulse. When the Q output of UL7A goes High,
it fires the 0.11 second oneshot, U23. Since the
AUTO/X1 line from J1 is Low, U24B enables U12E to
pass the .11 second pulse to the clock input of U1 7B. The
trailing edge ofthe pulse clocks U17B, causing the Q out-
put to go Low. This enables the next LOG pulse to
terminate the measurement by clocking U17A.
9H-4-20. Recall that a LOG pulse occurs for each 10N
event of the F2 signal; however, any LOG pulses that oc-
cur prior to setting U17B (a delay of 0.11 seconds) are
ignored. The measurement ends with the LOG pulse
that occurs immediately after U17B sets. This always
corresponds to a gate time between .11 s and 1.1 s, as
illustrated in Figure 9H-4-1.
9H-4-21. As an example in explaining the graph in
Figure 9H-4-1, assume a period average measurement is
being made with an input frequency of 400 Hz. One
period of 400 Hz is 1/400 = .0025 s = 2,5 ms. Since 10
periods must be counted to produce the first log pulse,
this pulse would occur after 25 ms (2.5 ms + 10). This log
pulse is ignored, since it falls within the 110 ms (.11 s)
delay of the one-shot. The next log pulse occurs 10 times
later at 250 ms (25 ms + 10). This pulse ends the
9H-4-2
measurement since the .11 s inhibit time has elapsed.
The gate time, then, is .25 s.
9H-4-22. Frequency A Mode
9H-4-23. Inthe frequency mode, the Channel A signal
is sent from U4(4) to the F1 switch (see Frequency Mode
Flow Diagram, Figure 9H-4-2). Gates U5E and U5D
couple the signal to USB(3) where it is gated to the
counting decades by the Auxiliary Gate FF, U17A.
9H-4-24. Prior to making a measurement, the
INHIBIT line resets U17A and B. The resultant Low on
the Q output of U17A prevents the Auxiliary Main Gate
from passing the Channel A signal to the counting
decades. At the end of the sample rate rundown, the
INHIBIT line returns High, followed by a LOG pulse.
Gates UTE, U7D, and U20B couple this pulse to the clock
input of UI7A. Clocking U17A transfers the High on the
D input to the Q output where it opens the Auxiliary
Main Gate at U8B(2). It also enables U12A and D and
places a Low on the clock input of U17B.
9H-4-25. The Channel A signal passes through the
High Speed Decade, Ul3 and 18, before entering the
mainframe on the F1 line. As the mainframe begins ac-
cumulating Fl counts, the mainframe's Time Base
Decades also begin accumulating 10 MHz clock pulses
via U21A and D. Once the Time Base Decades reach a
count equal to the selected gate time, a pulseis generated
on the TB OUT line that toggles U17B via Q8, U16C,
U12A and D The following LOG pulse is sent through
Q5, U24A, UTE and D, and U20B to close the Auxiliary
Gate FF, thereby closing the Auxiliary Main Gate.
9H-4-26. Frequency A/B Mode
9H-4-27. The frequency A/B mode performs a ratio
measurement between the Channel A and Channel B
frequencies. This mode is similar to the FREQ A mode,
since a frequency measurement is simply a ratio
between the Channel A frequency and the 10 MHz
internal clock. Instead of sending the 10 MHz clock to
the Time Base Decade, the counter substitutes the
Channel B signal. Refer to the Frequency A/B Mode
Flow Diagram, Figure 9H-4-3,
9H-4-28. At the beginning of the measurement, the
"time zero" LOG pulse clocks the AGFF(U17A) via UTE,
U7D, and U20B. The resultant High on the Q output
opens the Auxiliary Main Gate at USD and allows the
Channel A signal from U4A to pass through U5E and D
and U8B and D. From there, it passes through the High
Speed Decade and into the mainframe's counter assem-
bly via the Fl line. At the same time, the Channel B
signal enters the mainframe's Time Base Decade
through U21E and U21D.
9H-4-29. When the AGFF was set with the "time zero"
LOG pulse, it enabled UI2A and U12D and placed a Low
on the clock input of U17B. Once the Time Base Decades
reach a count equal to the selected gate time, a pulse is