Pioneer KRL-46V Service Manual page 65

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K4D263238K-VC40 GRAPHICS MEMORY GDDR SDRAM 128Mbit : Introduction (IC 3501, IC 3502)
The K4D263238K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words
by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe
allow extremely high performance up to 2.0GB/s/chip.
I/O transactions are possible on both edges of the clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful
for a variety of high performance memory system applications.
This memory is associated with Video-processor for graphics.
M2332FP DAC TUNER & BTR : Introduction (IC 2602)
Integrated circuit semiconductor of CMOS structure with 2 channels of built in D-A converters with output buffer
operational amplifiers. The input is 2-wires serial method is used for the transfer format of digital data to allow
connection with a microcomputer with minimum wiring. Digital Analogue converter for tuner gain and brightness of
inverter.
S29GL128 FLASH MEMORY 128Mbit : Introduction (IC 8701)
128 Megabit, 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit Process Technology, Package: 64 ball
BAG.
The Flash Memory stores the main program that is used for the CPU.
K4N56163QI-ZC2A GDDR2 SDRAM 256 Mbit : Introduction (IC 8301, IC 8302, IC 8303, IC 8304)
FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM
The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device.
This synchronous device achieve high speed graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for
general applications.
The chip is designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency - 1, Off-Chip Driver (OCD) impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion.
A thirteen bit address bus is used to convey row, column, and bank address information in a /RAS//CAS multiplexing
style.
This 4 memory is associated with CPU and MPEG-Decoder.
S24CS64A NVM 64Kb-E2PROM : Introduction (IC 8704)
The S24CS64A is a 2-wire (I2C bus type) serial EEPROM that is electrically programmable. NVM of Main CPU to store
the user data.
XC95288XL CPLD : Introduction (IC 9101)
The XC95288XL is a 3.3V CPLD targeted for high-performance, low voltage applications in leading-edge
communications and computing system. It is providing 6,400 usable gates with propagation delays of 6 ns.
This is for control of PC-CARD (Flash memory Card) to update software, reset for different micros, etc.
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