Page 1 Preliminary User’s Manual µ PD780973 Subseries 8-Bit Single-Chip Microcontrollers µ PD780973(A) µ PD78F0974 Document No. U12406EJ2V0UM00 (2nd edition) Date Published May 1998 N CP(K) © 1997 Printed in Japan...
Page 2 [MEMO]...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM, FIP, and IEBus are trademarks of NEC Corporation. Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 MAJOR REVISIONS IN THIS EDITION (1/2) Page Description p.38 Table 2-1. Pin Input/Output Circuit Types Correction of ports 8 and 9 input/output circuit types p.40 Figure 2-1. I/O Circuits of Pins Change of type 17-A to type 17-G p.54 Addition of oscillator mode register to Table 3-5. Special Function Register List p.67 4.1 EEPROM Functions Change of the number of rewrite frequency per 1 byte as follows:...
Page 7 MAJOR REVISIONS IN THIS EDITION (2/2) Page Description p.255 Addition of oscillator mode register to Table 21-1. Hardware Status after Reset Change of Note in Table 22-1. Differences between µ PD78F0974 and µ PD780973(A) p.257 p.279 APPENDIX A DEVELOPMENT TOOLS •...
Page 8 INTRODUCTION Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD780973 Subseries and design and develop its application systems and programs. Purpose This manual is designed to help users understand the following functions using the organization below.
Page 9 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Related documents for µ PD780973 Subseries Document No. Document Name Japanese English µ PD780973(A) Preliminary Product Information U12759J U12759E µ...
Page 10 English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electro Static Discharge (ESD)
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ........................1.1 Features ..........................1.2 Applications ......................... 1.3 Ordering Information ......................1.4 Quality Grade ........................1.5 Pin Configuration (Top View) ..................... 1.6 78K/0 Series Product Development ................... 1.7 Block Diagram ........................1.8 Outline of Function ......................CHAPTER 2 PIN FUNCTION ......................
Page 12 3.2.3 Special function registers (SFRs) ....................3.3 Instruction Address Addressing ..................3.3.1 Relative addressing ........................3.3.2 Immediate addressing ........................ 3.3.3 Table indirect addressing ......................3.3.4 Register addressing ........................3.4 Operand Address Addressing .................... 3.4.1 Implied addressing ........................3.4.2 Register addressing ........................3.4.3 Direct addressing ........................
Page 13 6.4 System Clock Oscillator ...................... 6.4.1 Main system clock oscillator ....................... 6.4.2 Divider circuit ..........................6.5 Operation of Clock Generator .................... 6.6 Changing Setting of CPU Clock ..................6.6.1 Time required for switching CPU clock ..................6.6.2 Switching CPU clock ........................CHAPTER 7 16-BIT TIMER 0 TM0 ....................
Page 14 11.4 Watchdog Timer Operations ....................143 11.4.1 Watchdog timer operation ......................11.4.2 Interval timer operation ....................... CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ..............145 12.1 Clock Output Control Circuit Functions ................145 12.2 Clock Output Control Circuit Configuration ..............145 12.3 Clock Output Control Circuit Control Registers ...............
Page 15 16.9 Cautions on Emulation ......................203 CHAPTER 17 SOUND GENERATOR ....................205 17.1 Sound Generator Function ....................205 17.2 Sound Generator Configuration ..................206 17.3 Sound Generator Control Registers .................. 207 17.4 Sound Generator Operations ..................... 212 17.4.1 To output basic cycle signal SGOF (without amplitude) ............. 17.4.2 To output basic cycle signal SGO (with amplitude) ..............
Page 16 CHAPTER 23 INSTRUCTION SET ....................263 23.1 Legend for Operation List ....................264 23.1.1 Operand identifiers and description formats ................23.1.2 Description of “operation” column ....................23.1.3 Description of “flag operation” column ..................23.2 Operation List ........................266 23.3 Instructions Listed by Addressing Type ................274 APPENDIX A DEVELOPMENT TOOLS ..................
Page 17 LIST OF FIGURES (1/4) Figure No. Title Page 2-1. I/O Circuits of Pins ..........................Memory Map ( µ PD780973(A)) ......................3-1. Memory Map ( µ PD78F0974) ......................3-2. Data Memory Addressing ( µ PD780973(A)) ..................3-3. Data Memory Addressing ( µ PD78F0974) ..................3-4.
Page 18 LIST OF FIGURES (2/4) Figure No. Title Page 7-7. CR0m Capture Operation with Rising Edge Specified ..............7-8. Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) ......................7-9. 16-Bit Timer Register Start Timing ....................7-10. Capture Register Data Retention Timing ..................
Page 19 LIST OF FIGURES (3/4) Figure No. Title Page 13-8. A/D Conversion ..........................13-9. Example of Method of Reducing Current Consumption in Standby Mode ........13-10. Analog Input Pin Connection ......................13-11. A/D Conversion End Interrupt Request Generation Timing .............. 13-12. D/A Converter Mode Register (DAM1) Format .................
Page 20 LIST OF FIGURES (4/4) Figure No. Title Page 18-1. Meter Controller/Driver Block Diagram ..................... 18-2. 1-Bit Addition Circuit Block Diagram ....................18-3. Timer Mode Control Register (MCNTC) Format ................18-4. Compare Control Register n (MCMPCn) Format ................18-5. Port Mode Control Register (PMC) Format ..................18-6.
Page 21 LIST OF TABLES (1/2) Table No. Title Page 2-1. Pin Input/Output Circuit Types ......................3-1. Internal Memory Capacity ......................... 3-2. Vector Table ............................3-3. Internal High-Speed RAM Capacity ....................3-4. Internal High-Speed RAM Area ......................3-5. Special Function Register List ......................5-1.
Page 22 LIST OF TABLES (2/2) Table No. Title Page 16-1. Maximum Number of Display Pixels ....................16-2. LCD Controller/Driver Configuration ....................16-3. COM Signals ............................. 16-4. LCD Drive Voltage ..........................16-5. LCD Drive Voltage ..........................16-6. Selection and Non-Selection Voltages (COM0 to COM3) ..............17-1.
Page 23: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features • Internal memory Item Program Memory Data Memory Part Number (ROM/Flash Memory) Internal High-Speed RAM LCD Display RAM EEPROM µ PD780973(A) 20 × 4 bits 24 Kbytes 768 bytes 256 bytes µ PD78F0974 32 Kbytes 1024 bytes High-speed instruction execution time (0.24 µ...
Page 24: Ordering Information
80-pin plastic QFP (14 × 20 mm) Special Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 25: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 20 mm) µ PD780973GF(A)-×××, 78F0974GF 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P87/S13 COM0 P86/S14 P85/S15 P84/S16 P83/S17 SM11/P20 P82/S18...
Page 26 CHAPTER 1 OUTLINE ANI0 to ANI4 : Analog Input : Serial Clock : Analog Reference Voltage : Sound Generator Output : Analog Ground SGOA : Sound Generator Amplitude Output COM0 to COM3 : Common Output SGOF : Sound Generator Frequency Output : Internally Connected : Serial Input INTP0 to INTP2 : Interrupt from Peripherals...
Page 27: Series Product Development
CHAPTER 1 OUTLINE 1.6 78K/0 Series Product Development These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus.
Page 28 CHAPTER 1 OUTLINE The major functional differences among the subseries are shown below. Function Timer 8-bit 10-bit 8-bit External Serial Interface MIN. Capacity A/D D/A Expansion 8-bit 16-bit Watch WDT Subseries Name Value µ PD78075B 32 K to 40 K Control 4 ch 1 ch...
Page 29: Block Diagram
CHAPTER 1 OUTLINE 1.7 Block Diagram 16-bit TIMER0 PORT0 TI00/P40 to TI02/P42 P00 to P07 PORT1 8-bit TIMER1 P10 to P14 8-bit TIMER/ TIO2/P43 EVENT PORT2 P20 to P27 COUNTER2 8-bit TIMER/ TIO3/P44 EVENT PORT3 P30 to P37 COUNTER3 WATCHDOG PORT4 P40 to P44 TIMER...
Page 30: Outline Of Function
CHAPTER 1 OUTLINE 1.8 Outline of Function Part Number µ PD780973(A) µ PD78F0974 Item Internal memory 24 Kbytes 32 Kbytes (Mask ROM) (Flash memory) Internal high-speed RAM 768 bytes 1024 bytes EEPROM 256 bytes 20 × 4 bits LCD display RAM 8 bits ×...
Page 31: Pin Function
CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1) Port Pins Alternate Pin Name Input/Output Function After Reset Function Port 0 P00 to P02 Input/Output Input INTP0 to INTP2 8-bit input/output port. P03 to P07 — Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software.
Page 32 CHAPTER 2 PIN FUNCTION (2) Non-port pins Alternate Pin Name Input/Output Function After Reset Function INTP0 to INTP2 Input External interrupt request input with specifiable valid edges Input P00 to P02 (rising edge, falling edge, both rising and falling edges). Input Serial interface serial data input.
Page 33: Description Of Pin Functions
CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit input/output port. In addition, they are also used to input external interrupt request signals. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P00 to P07 function as an 8-bit input/output port.
Page 34: P30 To P37 (Port 3)
CHAPTER 2 PIN FUNCTION 2.2.4 P30 to P37 (Port 3) These pins constitute an 8-bit output only port. In addition, they also function as PWM output pins to control meters. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P30 to P37 function as an 8-bit output only port.
Page 35: P60, P61 (Port 6)
CHAPTER 2 PIN FUNCTION (c) SCK Serial interface serial clock input/output pin. (d) RxD, TxD Asynchronous serial interface serial data input/output pins. 2.2.7 P60, P61 (Port 6) These pins constitute a 2-bit input/output port. In addition, they also function as clock output and sound generator output pins.
Page 36: P90 To P97 (Port 9)
CHAPTER 2 PIN FUNCTION 2.2.9 P90 to P97 (Port 9) These pins constitute an 8-bit input/output port. In addition, they also function to output segment signals from the internal LCD controller/driver. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P90 to P97 function as an 8-bit input/output port.
Page 37: Pp ( Μ Pd78F0974)
CHAPTER 2 PIN FUNCTION ( µ PD78F0974) 2.2.20 V A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Directly connect this pin to V in the normal operating mode.
Page 38: Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTION 2.3 Input/output Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of pins and the recommended connection for unused pins. Refer to Figure 2-1 for the configuration of the input/output circuit of each type. Table 2-1.
Page 39 CHAPTER 2 PIN FUNCTION Figure 2-1. I/O Circuits of Pins (1/2) Type 2 Type 8 data P-ch IN/OUT output N-ch disable Schmitt-triggered input with hysteresis characteristics Type 4 Type 8-A pullup P-ch enable data P-ch data P-ch IN/OUT output N-ch output disable N-ch...
Page 40 CHAPTER 2 PIN FUNCTION Figure 2-1. I/O Circuits of Pins (2/2) Type 17 Type 17-G P-ch N-ch data P-ch P-ch IN/OUT data output N-ch N-ch P-ch disable N-ch input enable Type 18 P-ch N-ch P-ch P-ch N-ch N-ch data P-ch N-ch P-ch N-ch...
Page 41: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces The µ PD780973 Subseries can access a 64-Kbyte memory space. Figures 3-1 and 3-2 show memory maps of the respective devices. Figure 3-1. Memory Map ( µ PD780973(A)) FFFFH Special Function Registers (SFRs) 256 ×...
Page 42 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ PD78F0974) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1024 × 8 bits FB00H FAFFH Reserved FA6DH FA6CH 7FFFH...
Page 43: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The µ PD780973 Subseries incorporate internal ROM (or flash memory), as listed below. Table 3-1.
Page 44: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space The µ...
Page 45: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 3.3 Instruction Address Addressing).
Page 46 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Data Memory Addressing ( µ PD78F0974) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1024 ×...
Page 47: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD780973 Subseries incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, status, and stack memory. The control registers consist of a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 48 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to DI, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to EI and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specify flag.
Page 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented prior to write (save) to the stack memory and is incremented after read (restore) from the stack memory.
Page 50: General Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General registers General registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. Four banks of general registers, each consisting of eight 8-bit registers (X, A, C, B, E, D, L and H) are available. Each register can also be used as an 8-bit register.
Page 51: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general registers, these registers have special functions. They are allocated in the FF00H to FFFFH area. The special-function registers can be manipulated like the general registers, with the operation, transfer and bit manipulation instructions.
Page 52 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits FF00H Port 0 — FF01H Port 1 — — Note FF02H Port 2 —...
Page 53 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits FF20H Port mode register 0 — FF22H Port mode register 2 — FF23H Port mode register 3 —...
Page 54 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits FF76H 8-bit timer mode control register 1 TMC1 — FF77H 8-bit timer mode control register 2 TMC2 —...
Page 55: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 56: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 57: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 58: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.
Page 59: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general register to be specified is accessed as an operand with the register specify code (Rn and RPn) in an operation code and with the register bank select flags (RBS0 and RBS1). Register addressing is carried out when an instruction with the following operand format is executed.
Page 60: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 61: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal high-speed RAM and a special- function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 62: Special-Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special-function register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 63: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] This addressing is to address a memory area to be manipulated by using as an operand address the contents of a register pair specified by the register bank select flags (RBS0 and RBS1) and the register pair specification code in the operation code.
Page 64: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flags (RBS0 and RBS1) and the sum is used to address the memory.
Page 65: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only.
Page 66 [MEMO]...
Page 67: Chapter 4 Eeprom
Caution The values shown above are target values. These values are subject to change without notice, so please contact your NEC sales representative for the latest value before designing. (4) When write is completed, interrupt request signal (INTWE) is issued.
Page 68: Eeprom Configuration
CHAPTER 4 EEPROM 4.2 EEPROM Configuration EEPROM is composed of EEPROM itself and a control area. The control area consists of the EEPROM write control register (EEWC) that controls EEPROM writing, and an area that generates an interrupt request signal (INTWE) upon detecting write termination. Figure 4-1.
Page 69: Eeprom Control Register
CHAPTER 4 EEPROM 4.3 EEPROM Control Register EEPROM is controlled with the EEPROM write control register (EEWC). EEWC is set with either a 1-bit or 8-bit memory manipulation instruction. RESET input sets EEWC to 00H. Figure 4-2. EEPROM Write Control Register (EEWC) Format Address: FF90H After Reset : 00H Symbol EEWC...
Page 70: Eeprom Reading
CHAPTER 4 EEPROM 4.4 EEPROM Reading Reading of EEPROM data is performed with the following procedure. <1> Check that EWST (EEPROM write control register (EEWC) bit 1) is 0 (EEPROM writing is not in progress). <2> Execute read instruction. Cautions 1. Before reading, be sure to check that EWST is 0. If an EEPROM read instruction is executed during EEPROM write, read values are undefined.
Page 71: Eeprom Writing
CHAPTER 4 EEPROM 4.5 EEPROM Writing Data writing to EEPROM is performed with the following procedure. <1> Check that EWST (EEPROM write control register (EEWC) bit 1) is 0 (EEPROM writing is not in progress). <2> Set the write time with EWCS0 and EWCS1 (EEWC bits 4 and 5). <3>...
Page 72: Cautions Regarding Eeprom Writing
CHAPTER 4 EEPROM 4.7 Cautions regarding EEPROM Writing The following shows cautions of EEPROM write. Before performing EEPROM write, be sure to read the following cautions. (1) Before writing, be sure to check that EWST (EEPROM write control register (EEWC) bit 1) is 0. If executing another write instructions during EEPROM writing, the instruction executed last will be ignored.
Page 73: Chapter 5 Port Functions
CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions The µ PD780973 Subseries are provided with five input port pins, sixteen output port pins, and thirty-five input/output port pins. Figure 5-1 shows the port configuration. Every port can be manipulated in 1-bit or 8-bit units controlled in various ways.
Page 74 CHAPTER 5 PORT FUNCTIONS Table 5-1. Port Functions Alternate Pin Name Input/Output Function Function P00 to P02 Input/Output Port 0 INTP0 to INTP2 8-bit input/output port. P03 to P07 — Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software.
Page 75: Port Configuration
CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration A port consists of the following hardware: Table 5-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 2 to 6, 8, 9) Pull-up resistor option register (PU0) Port Total: 56 lines (5 inputs, 16 outputs, 35 inputs/outputs) Pull-up resistor Total: 8 (software specifiable: 8)
Page 76: Port 1
CHAPTER 5 PORT FUNCTIONS Figure 5-2. P00 to P07 Block Diagram PU00 to PU07 P-ch Selector PORT P00/INTP0 Output latch (P00 to P07) P02/INTP2 P03 to P07 PM00 to PM07 PU : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal 5.2.2 Port 1...
Page 77: Port 2
CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an 8-bit output only port with output latch. P20 to P27 pins go into a high-impedance state when the ENn of port mode control register (PMC) is set to 0 and the port mode register 2 (PM2) is set to 1. Alternate functions include meter control PWM output.
Page 78: Port 3
CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is an 8-bit output only port with output latch. P30 to P37 pins go into a high-impedance state when the ENn of port mode control register (PMC) is set to 0 and the port mode register 3 (PM3) is set to 1. Alternate functions include meter control PWM output.
Page 79: Port 4
CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 4 Port 4 is a 5-bit input/output port with output latch. P40 to P44 pins can specify the input mode/output mode in 1-bit units with the port mode register 4 (PM4). Alternate functions also include timer input/output. RESET input sets port 4 to input mode.
Page 80: Port 5
CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 5 Port 5 is a 5-bit input/output port with output latch. P50 to P54 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). Alternate functions include serial interface data input/output and clock input/output. RESET input sets port 5 to input mode.
Page 81: Port 6
CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 6 Port 6 is a 2-bit input/output port with output latch. P60 and P61 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). Alternate functions include clock output and sound generator output. RESET input sets port 6 to input mode.
Page 82: Port 8
CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 8 Port 8 is a 7-bit input/output port with output latch. P81 to P87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (PM8). Alternate functions also include segment signal output of the LCD controller/driver and prescaler signal output. Segment output and input/output port can be switched by setting the LCD display control register (LCDC).
Page 83: Port 9
CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 9 Port 9 is an 8-bit input/output port with output latch. P90 to P97 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (PM9). Alternate functions also include segment signal output of the LCD controller/driver. Segment output and input/output port can be switched by setting the LCD display control register (LCDC).
Page 84: Port Function Control Registers
CHAPTER 5 PORT FUNCTIONS 5.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM2 to PM6, PM8, PM9) • Pull-up resistor option register (PU0) (1) Port mode registers (PM0, PM2 to PM6, PM8, PM9) These registers are used to set port input/output in 1-bit units.
Page 85 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Mode Register and Output Latch Settings when Using Alternate Functions Alternate Functions PM×× P×× Pin Name Name Input/Output × INTP0 Input × INTP1 Input × INTP2 Input × Note 1 P10 to P14 ANI0 to ANI4 Input ×...
Page 86 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Port Mode Register (PM0, PM4 to PM6, PM8, PM9) Format Address: FF20H After Reset : FFH Symbol PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FF24H After Reset : FFH Symbol PM44 PM43 PM42 PM41 PM40...
Page 87 CHAPTER 5 PORT FUNCTIONS (2) Pull-up resistor option register (PU0) This register is used to set whether to use an internal pull-up resistor at port 0 or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with PU0. No pull-up resistors can be used to the bits set to the output mode irrespective of PU0 setting.
Page 88: Port Function Operations
CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 89: Chapter 6 Clock Generator
CHAPTER 6 CLOCK GENERATOR 6.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. • Main system clock oscillator This circuit oscillates at frequencies of 4.19 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 90: Clock Generator Control Register
CHAPTER 6 CLOCK GENERATOR 6.3 Clock Generator Control Register The following two types of registers are used to control the clock generator. • Processor clock control register (PCC) • Oscillator mode register (OSCM) (1) Processor clock control register (PCC) The PCC sets the division ratio of the CPU clock. The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 91 CHAPTER 6 CLOCK GENERATOR (2) Oscillator mode register (OSCM) The µ PD780973(A) can be set to the reduced current consumption mode by setting OSCM (only when operated at f = 4 to 4.19 MHz). OSCM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets OSCM to 00H.
Page 92: System Clock Oscillator
CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.38 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an inverted clock signal to the X2 pin.
Page 93 CHAPTER 6 CLOCK GENERATOR Caution When using a main system clock oscillator, carry out wiring in the broken line area in Figure 6-4 as follows to avoid influence of wiring capacity. • Keep the wiring length as short as possible. •...
Page 94: Divider Circuit
CHAPTER 6 CLOCK GENERATOR Figure 6-5. Incorrect Examples of Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched 6.4.2 Divider circuit The divider circuit divides the output of the main system clock oscillation circuit (f ) to generate various clocks.
Page 95: Operation Of Clock Generator
CHAPTER 6 CLOCK GENERATOR 6.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode: • Main system clock • CPU clock • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and oscillator mode register (OSCM) as follows: (a) The slowest mode (3.81 µ...
Page 96: Changing Setting Of Cpu Clock
CHAPTER 6 CLOCK GENERATOR 6.6 Changing Setting of CPU Clock 6.6.1 Time required for switching CPU clock The CPU clock can be selected by using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (refer to Table 6-3).
Page 97: Switching Cpu Clock
CHAPTER 6 CLOCK GENERATOR 6.6.2 Switching CPU clock The following figure illustrates how the CPU clock switches. Figure 6-6. Switching CPU Clock RESET CPU clock Slowest Fastest operation operation Wait (15.6 ms: at 8.38-MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating.
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Page 99: Chapter 7 16-Bit Timer 0 Tm0
CHAPTER 7 16-BIT TIMER 0 TM0 7.1 Outline of Internal Timer of µ PD780973 Subseries This chapter explains the 16-bit timer 0. Before that, the internal timers of the µ PD780973 Subseries, and the related functions are briefly explained below. (1) 16-bit timer 0 TM0 The TM0 can be used for pulse widths measurement, divided output of input pulse.
Page 100: 16-Bit Timer 0 Functions
CHAPTER 7 16-BIT TIMER 0 TM0 Table 7-1. Timer/Event Counter Operations 8-bit Timer/Event 16-bit Timer TM0 8-bit Timer TM1 Watch Timer Watchdog Timer Counter TM2, TM3 Note 1 Note 2 Operating Interval timer – 1 channel 2 channels 1 channel 1 channel mode External event counter...
Page 101 CHAPTER 7 16-BIT TIMER 0 TM0 Figure 7-1. Timer 0 (TM0) Block Diagram Internal bus Prescaler mode Capture pulse control 16-bit timer mode control register (PRM0) register (CRC0) register (TMC0) ES21 ES20 ES11 ES10 ES01 ES00 PRM01 PRM00 CRC01 CRC00 TMC02 TPOE 16-bit timer register (TM0) INTOVF...
Page 102: 16-Bit Timer 0 Configuration
CHAPTER 7 16-BIT TIMER 0 TM0 7.3 16-Bit Timer 0 Configuration Timer 0 consists of the following hardware. Table 7-2. Timer 0 Configuration Item Configuration 16 bits × 1 (TM0) Timer register Capture register: 16 bits × 3 (CR00 to CR02) Register Control register 16-bit timer mode control register (TMC0)
Page 103: 16-Bit Timer 0 Control Registers
CHAPTER 7 16-BIT TIMER 0 TM0 7.4 16-Bit Timer 0 Control Registers The following three types of registers are used to control timer 0. • 16-bit timer mode control register (TMC0) • Capture pulse control register (CRC0) • Prescaler mode register (PRM0) (1) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode and controls the prescaler output signals.
Page 104 CHAPTER 7 16-BIT TIMER 0 TM0 (2) Capture pulse control register (CRC0) This register specifies the division ratio of the capture pulse input to the 16-bit capture register (CR02) from an external source. CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H.
Page 105 CHAPTER 7 16-BIT TIMER 0 TM0 (3) Prescaler mode register (PRM0) This register is used to set 16-bit timer (TM0) count clock and valid edge of TI0n (n = 0 to 2) input. PRM0 is set with an 8-bit memory manipulation instruction. RESET input sets PRM0 value to 00H.
Page 106: 16-Bit Timer 0 Operations
CHAPTER 7 16-BIT TIMER 0 TM0 7.5 16-Bit Timer 0 Operations 7.5.1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P40 to TI02/P42 pins using the 16-bit timer register (TM0). TM0 is used in free-running mode. (1) Pulse width measurement with free-running counter and one capture register (TI00) When the edge specified by prescaler mode register (PRM0) is input to the TI00/P40 pin, the value of TM0 is taken into 16-bit capture register 00 (CR00) and an external interrupt request signal (INTTM00) is set.
Page 107 CHAPTER 7 16-BIT TIMER 0 TM0 (2) Measurement of three pulse widths with free-running counter The 16-bit timer register (TM0) allows simultaneous measurement of the pulse widths of the three signals input to the TI00/P40 to TI02/P42 pins. When the edge specified by bits 2 and 3 (ES00 and ES01) of prescaler mode register (PRM0) is input to the TI00/P40 pin, the value of TM0 is taken into 16-bit capture register 00 (CR00) and an external interrupt request signal (INTTM00) is set.
Page 108 CHAPTER 7 16-BIT TIMER 0 TM0 Figure 7-8. Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H FFFFH 0000H TM0 count value TI0m pin input Value loaded to CR0m INTTM0m TI0n pin input Value loaded to CR0n INTTM0n INTOVF...
Page 109: 16-Bit Timer 0 Cautions
CHAPTER 7 16-BIT TIMER 0 TM0 7.6 16-Bit Timer 0 Cautions (1) Timer start errors An error with a maximum of one clock may occur until counting is started after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 7-9.
Page 110 CHAPTER 7 16-BIT TIMER 0 TM0 (4) Occurrence of INTTM0n INTTM0n occurs even if no capture pulse exists, immediately after the timer operation has been started (TMC02 of TMC0 has been set to 1) with a high level applied to input pins TI00 to TI02 of 16-bit timer 0, and with the rising edge (with ESn1 and ESn0 of PRM0 set to 0, 1), or both the rising and falling edges (with ESn1 and ESn0 of PRM0 set to 1, 1) selected.
Page 111: Chapter 8 8-Bit Timer 1 Tm1
CHAPTER 8 8-BIT TIMER 1 TM1 8.1 8-Bit Timer 1 Functions The 8-bit timer 1 operates as an 8-bit interval timer. Figure 8-1 shows timer 1 block diagram. Figure 8-1. Timer 1 (TM1) Block Diagram Internal bus 8-bit compare register 1 (CR1) Coincidence INTTM1 8-bit counter (TM1)
Page 112: 8-Bit Timer 1 Configuration
CHAPTER 8 8-BIT TIMER 1 TM1 8.2 8-Bit Timer 1 Configuration Timer 1 consists of the following hardware. Table 8-1. Timer 1 Configuration Item Configuration Timer register 8-bit counter 1 (TM1) Register 8-bit compare register 1 (CR1) Control register Timer clock select register 1 (TCL1) 8-bit timer mode control register 1 (TMC1) Remark n = 0, 1 (1) 8-bit counter 1 (TM1)
Page 113: 8-Bit Timer 1 Control Registers
CHAPTER 8 8-BIT TIMER 1 TM1 8.3 8-Bit Timer 1 Control Registers The following two types of registers are used to control timer 1. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) (1) Timer clock select register 1 (TCL1) This register sets count clocks of timer 1.
Page 114 CHAPTER 8 8-BIT TIMER 1 TM1 (2) 8-bit timer mode control register 1 (TMC1) TMC1 is a register that controls the counting operation of the 8-bit counter 1 (TM1). TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets to 04H.
Page 115: 8-Bit Timer 1 Operations
CHAPTER 8 8-BIT TIMER 1 TM1 8.4 8-Bit Timer 1 Operations 8.4.1 8-bit interval timer operation The 8-bit timer 1 operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register 1 (CR1). When the count values of the 8-bit counter 1 (TM1) match the values set to CR1, counting continues with the TM1 values cleared to 0 and the interrupt request signal (INTTM1) is generated.
Page 116 CHAPTER 8 8-BIT TIMER 1 TM1 Figure 8-4. Interval Timer Operation Timings (2/3) (b) When CR1 = 00H Count clock TCE1 INTTM1 TM1 interval time Interval time (c) When CR1 = FFH Count clock TCE1 INTTM1 Interrupt received Interrupt received TM1 interval time Interval time...
Page 117 CHAPTER 8 8-BIT TIMER 1 TM1 Figure 8-4. Interval Timer Operation Timings (3/3) (d) Operated by CR1 transition (M < N) Count clock TCE1 INTTM1 TM1 interval time CR1 transition TM1 overflows since M < N (e) Operated by CR1 transition (M > N) Count clock N–1 M–1...
Page 118: 8-Bit Timer 1 Cautions
CHAPTER 8 8-BIT TIMER 1 TM1 8.5 8-Bit Timer 1 Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit counter 1 (TM1) is started asynchronously with the count pulse. Figure 8-5.
Page 119: Chapter 9 8-Bit Timer/Event Counters 2, 3 Tm2, Tm3
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.1 8-Bit Timer/Event Counters 2 and 3 Functions The 8-bit timer/event counters 2 and 3 operate as an 8-bit timer/event counter. TM2 and TM3 can have the following functions. • Interval timer •...
Page 120 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-2. Timer 3 (TM3) Block Diagram Internal bus 8-bit compare Selector INTTM3 register 3 (CR3) TIO3/P44 Coincidence 8-bit counter 3 TIO3/P44 (TM3) Note Clear P44 output latch PM44 Invert level Selector TCE3 TMC36 LVS3 LVR3 TMC31 TOE3 TCL32 TCL31 TCL30...
Page 121: 8-Bit Timer/Event Counters 2 And 3 Configurations
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.2 8-Bit Timer/Event Counters 2 and 3 Configurations Timers 2 and 3 consist of the following hardware. Table 9-1. Timers 2 and 3 Configurations Item Configuration Timer register 8-bit counter n (TMn) Register 8-bit compare register n (CRn) Timer output...
Page 122: 8-Bit Timer/Event Counters 2 And 3 Control Registers
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.3 8-Bit Timer/Event Counters 2 and 3 Control Registers The following two types of registers are used to control timers 2 and 3. • Timer clock select register n (TCLn) • 8-bit timer mode control register n (TMCn) n = 2, 3 (1) Timer clock select register n (TCLn: n = 2, 3) This register sets count clocks of timers 2 and 3.
Page 123 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-4. Timer Clock Select Register 3 (TCL3) Format Address: FF75H After Reset: 00H Symbol TCL3 TCL32 TCL31 TCL30 TCL32 TCL31 TCL30 Count Clock Selection TIO3 Falling edge TIO3 Rising edge (523 kHz) (130 kHz) (65.4 kHz)
Page 124 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-5. 8-Bit Timer Mode Control Register n (TMCn) Format Address: FF77H (TMC2) FF78H (TMC3) After Reset: 04H Symbol TMCn TCEn TMCn6 LVSn LVRn TMCn1 TOEn TCEn TM2, TM3 Count Operation Control After clearing counter to 0, count operation disabled (prescaler disabled) Count operation start TMCn6...
Page 125: 8-Bit Timer/Event Counters 2 And 3 Operations
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.4 8-Bit Timer/Event Counters 2 and 3 Operations 9.4.1 8-bit interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register n (CRn). When the count values of the 8-bit counter n (TMn) match the values set to CRn, counting continues with the TMn values cleared to 0 and the interrupt request signal (INTTMn) is generated.
Page 126 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-6. Interval Timer Operation Timings (2/3) (b) When CRn = 00H Count clock TCEn INTTMn TIOn Interval time (c) When CRn = FFH Count clock TCEn INTTMn Interrupt received Interrupt received TIOn Interval time...
Page 127: External Event Counter Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-6. Interval Timer Operation Timings (3/3) (d) Operated by CRn transition (M < N) Count clock TCEn INTTMn TIOn CRn transition TMn overflows since M < N (e) Operated by CRn transition (M > N) Count clock N–1 M–1...
Page 128: Square-Wave Output Operation (8-Bit Resolution)
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-7. External Event Counter Operation Timings (with Rising Edge Specified) TIOn TMn count value 0000 0001 0002 0003 0004 0005 N–1 0000 0001 0002 0003 INTTMn n = 2, 3 9.4.3 Square-wave output operation (8-bit resolution) A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare register n (CRn).
Page 129: 8-Bit Pwm Output Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.4.4 8-bit PWM output operation 8-bit timer/event counters operate as PWM output when bit 6 (TMCn6) of 8-bit timer mode control register n (TMCn) is set to 1. The duty rate pulse determined by the value set to 8-bit compare register n (CRn) is output from TIOn. Set the active level width of PWM pulse to CRn, and the active level can be selected with bit 1 (TMCn1) of TMCn.
Page 130 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 (a) PWM output basic operation Figure 9-8. PWM Output Operation Timing (i) Basic operation (active level = H) Count clock 00H 01H FFH 00H 01H 02H N N+1 FFH 00H 01H 02H TCEn INTTMn TIOn...
Page 131 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 (b) Operation by change of CRn Figure 9-9. Timing of Operation by Change of CRn (i) Change of CRn value to N to M before overflow of TMn Count clock N N+1 N+2 FFH 00H 01H M M+1 M+2 FFH 00H 01H 02H...
Page 132: 8-Bit Timer/Event Counters 2 And 3 Cautions
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.5 8-Bit Timer/Event Counters 2 and 3 Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start.
Page 133: Chapter 10 Watch Timer
CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows watch timer block diagram. Figure 10-1. Watch Timer Block Diagram 5-bit counter INTWT Clear...
Page 134: Watch Timer Configuration
CHAPTER 10 WATCH TIMER (1) Watch timer When the main system clock is used, interrupt requests (INTWT) are generated at 0.25 second (at f = 8.38- MHz operation) intervals. (2) Interval timer Interrupt requests (INTWT) are generated at the preset time interval. Table 10-1.
Page 135: Watch Timer Control Register
CHAPTER 10 WATCH TIMER 10.3 Watch Timer Control Register The watch timer mode control register (WTM) is used to control the watch timer. • Watch timer mode control register (WTM) This register sets the watch timer count clock, operation enable/disable, prescaler interval time and 5-bit counter operation control.
Page 136: Watch Timer Operations
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 8.38-MHz main system clock is used, the timer operates as a watch timer with a 0.25-second interval. The watch timer generates interrupt requests at a constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register are set to 1, the count operation starts.
Page 137 CHAPTER 10 WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.25 s) Interrupt time of watch timer (0.25 s) Interval timer interrupt INTWTI Interval timer Remark f...
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Page 139: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). Figure 11-1 shows the watchdog timer block diagram. Figure 11-1.
Page 140 CHAPTER 11 WATCHDOG TIMER (1) Watchdog timer mode A runaway is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 11-1. Watchdog Timer Runaway Detection Time Runaway Detection Time (489 µ s) × 1/f ×...
Page 141: Watchdog Timer Configuration
CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Control register Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer.
Page 142 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register (WDTM) Format Address: FFF9H After Reset: 00H Symbol...
Page 143: Watchdog Timer Operations
CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaways. Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set runaway time interval.
Page 144: Interval Timer Operation
CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt request repeatedly at an interval of the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are set to 1 and 0, respectively.
Page 145: Chapter 12 Clock Output Control Circuit
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output from the PCL/SGOA/P60 pin.
Page 146: Clock Output Control Circuit Control Registers
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Control Circuit Control Registers The following two types of registers are used to control the CKU. • Clock output selection register (CKS) • Port mode register 6 (PM6) (1) Clock output selection register (CKS) This register sets output clock.
Page 147 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT (2) Port mode register 6 (PM6) This register sets port 6 input/output in 1-bit units. When using the P60/PCL/SGOA pin for clock output, set PM60 and the output latch of P60 to 0. PM6 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM6 to FFH.
Page 148: Clock Output Control Circuit Operation
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.4 Clock Output Control Circuit Operation 12.4.1 Clock output operation To output the clock pulse, follow the procedure described below. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).
Page 149: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 A/D Converter Functions The A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 5 analog input channels (ANI0 to ANI4). This A/D converter has the following functions: (1) A/D conversion with 8-bit resolution One channel of analog input is selected from ANI0 to ANI4, and A/D conversion is repeatedly executed with a resolution of 8 bits.
Page 150: A/D Converter Configuration
CHAPTER 13 A/D CONVERTER Figure 13-2. Power-Fail Detection Function Block Diagram PFCM PFEN ANI0/P10 INTAD ANI1/P11 ANI2/P12 A/D converter Comparator ANI3/P13 ANI4/P14 Power-fail compare threshold value PFEN PFCM register (PFT) Power-fail compare mode register (PFM) Internal bus 13.2 A/D Converter Configuration A/D converter consists of the following hardware.
Page 151 CHAPTER 13 A/D CONVERTER (3) Sample & hold circuit The sample & hold circuit samples each analog input sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage.
Page 152: A/D Converter Control Registers
CHAPTER 13 A/D CONVERTER 13.3 A/D Converter Control Registers The following 4 types of registers are used to control A/D converter. • A/D converter mode register (ADM1) • Analog input channel specification register (ADS1) • Power-fail compare mode register (PFM) •...
Page 153 CHAPTER 13 A/D CONVERTER (2) Analog input channel specification register (ADS1) This register specifies the analog voltage input port for A/D conversion. ADS1 is set with an 8-bit memory manipulation instruction. RESET input clears ADS1 to 00H. Figure 13-4. Analog Input Channel Specification Register (ADS1) Format Address: FF81H After Reset: 00H R/W Symbol ADS1...
Page 154 CHAPTER 13 A/D CONVERTER (3) Power-fail compare mode register (PFM) The power-fail compare mode register (PFM) controls a comparison operation. RESET input clears PFM to 00H. Figure 13-5. Power-Fail Compare Mode Register (PFM) Format Address: FF82H After Reset: 00H R/W Symbol PFEN PFCM...
Page 155: A/D Converter Operations
CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS1). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 156 CHAPTER 13 A/D CONVERTER Figure 13-6. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR1 result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode register (ADM1) is reset (to 0) by software.
Page 157: Input Voltage And Conversion Results
CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI4) and the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is shown by the following expression. ×...
Page 158: A/D Converter Operation Mode
CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI4 with the analog input channel specification register (ADS1) and A/D conversion is performed. The following two types of functions can be selected by setting the PFEN flag of the PFM register.
Page 159 CHAPTER 13 A/D CONVERTER Figure 13-8. A/D Conversion ADM1 rewrite ADCS1 = 1 ADS1 rewrite ADCS1 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Stop Conversion results are not stored ADCR1 ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied...
Page 160: A/D Converter Cautions
CHAPTER 13 A/D CONVERTER 13.5 A/D Converter Cautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop conversion. Figure 13-9 shows how to reduce the current consumption in the standby mode.
Page 161 CHAPTER 13 A/D CONVERTER (4) Noise countermeasures To maintain 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI4. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 13-10 to reduce noise.
Page 162 CHAPTER 13 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS1) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS1 rewrite, and when ADIF is read immediately after the ADS1 rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended.
Page 163: Cautions On Emulation
CHAPTER 13 A/D CONVERTER 13.6 Cautions on Emulation (1) D/A converter mode register (DAM1) To perform debugging with an in-circuit emulator (IE-78K0-NS), the D/A converter mode register (DAM1) must be set. DAM1 is a register used to set a probe board (IE-780974-NS-EM1). DAM1 is used when the power-fail detection function is used.
Page 164 [MEMO]...
Page 165: Chapter 14 Serial Interface Uart
CHAPTER 14 SERIAL INTERFACE UART 14.1 UART Functions The serial interface UART has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit.
Page 166: Uart Configuration
CHAPTER 14 SERIAL INTERFACE UART 14.2 UART Configuration The UART consists of the following hardware. Table 14-1. UART Configuration Item Configuration Registers Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Control registers Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) (1) Transmit shift register (TXS)
Page 167: Uart Control Registers
CHAPTER 14 SERIAL INTERFACE UART (5) Receive control circuit The receive control circuit controls receive operations based on the values set to the asynchronous serial interface mode register (ASIM). During a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (ASIS) according to the type of error that is detected.
Page 168 CHAPTER 14 SERIAL INTERFACE UART Figure 14-2. Asynchronous Serial Interface Mode Register (ASIM) Format Address: FF85H After Reset: 00H Symbol ASIM ISRM Operation Mode Operation stop UART mode (receive only) UART mode (transmit only) UART mode (transmit and receive) Parity Bit Specification No parity Zero parity always added during transmission No parity detection during reception (parity errors do not occur)
Page 169 CHAPTER 14 SERIAL INTERFACE UART (2) Asynchronous serial interface status register (ASIS) When a receive error occurs during UART mode, this register indicates the type of error. ASIS is read with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-3.
Page 170 CHAPTER 14 SERIAL INTERFACE UART Figure 14-4. Baud Rate Generator Control Register (BRGC) Format Address: FF87H After Reset: 00H Symbol BRGC TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 = 8.38 MHz) TPS2 TPS1 TPS0 Source Clock Selection for 5-bit Counter MDL3 MDL2 MDL1...
Page 171: Uart Operations
CHAPTER 14 SERIAL INTERFACE UART 14.4 UART Operations This section explains the two modes of the UART. 14.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, P53/RxD and P54/TxD pins can be used as ordinary ports. (1) Register settings Operation stop mode settings are made via the asynchronous serial interface mode register (ASIM).
Page 172 CHAPTER 14 SERIAL INTERFACE UART (a) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Caution In UART mode, set the port mode register (PM5X) as follows. Besides that, set all output latches to 0.
Page 173 CHAPTER 14 SERIAL INTERFACE UART (b) Asynchronous serial interface status register (ASIS) ASIS is read with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Address: FF86H After Reset: 00H Symbol ASIS Parity Error Flag No parity error Parity error (Transmit data parity does not match) Framing Error Flag...
Page 174 CHAPTER 14 SERIAL INTERFACE UART (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Address: FF87H After Reset: 00H Symbol BRGC TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0...
Page 175 CHAPTER 14 SERIAL INTERFACE UART The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Use of main system clock to generate a transmit/receive clock for baud rate The main system clock is divided to generate the transmit/receive clock. The baud rate generated by the main system clock is determined according to the following formula.
Page 176 CHAPTER 14 SERIAL INTERFACE UART • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Table 14-3 describes the relation between the main system clock and the baud rate and Figure 14-5 shows an example of a baud rate error tolerance range.
Page 177 CHAPTER 14 SERIAL INTERFACE UART (2) Communication operations (a) Data format As shown in Figure 14-6, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. The asynchronous serial interface mode register (ASIM) is used to set the character bit length, parity selection, and stop bit length within each data frame.
Page 178 CHAPTER 14 SERIAL INTERFACE UART (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
Page 179 CHAPTER 14 SERIAL INTERFACE UART (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS, thereby emptying TXS, after which a transmit completion interrupt (INTST) is issued.
Page 180 CHAPTER 14 SERIAL INTERFACE UART (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXE) of the asynchronous serial interface mode register (ASIM), and input via the RxD pin is sampled. The serial clock specified by ASIM is used when sampling the RxD pin. When the RxD pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
Page 181 CHAPTER 14 SERIAL INTERFACE UART (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to the asynchronous serial interface status register (ASIS), a receive error interrupt (INTSER) will occur.
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Page 183: Chapter 15 Serial Interface Sio3
CHAPTER 15 SERIAL INTERFACE SIO3 15.1 SIO3 Functions The serial interface SIO3 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 15.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK), serial output line (SO), and serial input line (SI).
Page 184: Sio3 Configuration
CHAPTER 15 SERIAL INTERFACE SIO3 15.2 SIO3 Configuration The SIO3 consists of the following hardware. Table 15-1. SIO3 Configuration Item Configuration Register Serial I/O shift register (SIO) Control register Serial operation mode register (CSIM) (1) Serial I/O shift register (SIO) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.
Page 185: Sio3 Control Register
CHAPTER 15 SERIAL INTERFACE SIO3 15.3 SIO3 Control Register The SIO3 uses the following type of register for control functions. • Serial operation mode register (CSIM) (1) Serial operation mode register (CSIM) This register is used to enable or disable SIO3’s serial clock, operation modes, and specific operations. CSIM is set with a 1-bit or 8-bit memory manipulation instruction.
Page 186: Sio3 Operations
CHAPTER 15 SERIAL INTERFACE SIO3 15.4 SIO3 Operations This section explains the two modes of the SIO3. 15.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, the P50/SCK, P51/SO, and P52/SI pins can be used as normal I/O ports as well. (1) Register settings Operation stop mode are set via serial operation mode register (CSIM).
Page 187: Three-Wire Serial I/O Mode
CHAPTER 15 SERIAL INTERFACE SIO3 15.4.2 Three-wire serial I/O mode The three-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK), serial output line (SO), and serial input line (SI).
Page 188 CHAPTER 15 SERIAL INTERFACE SIO3 (2) Communication operations In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronized with the serial clock. The serial I/O shift register (SIO) is shifted in synchronized with the falling edge of the serial clock. Transmission data is held in the SO latch and is output from the SO pin.
Page 189: Chapter 16 Lcd Controller/Driver
CHAPTER 16 LCD CONTROLLER/DRIVER 16.1 LCD Controller/Driver Functions The functions of the LCD controller/driver incorporated in the µ PD780973 Subseries are shown below. (1) Automatic output of segment signals and common signals is possible by automatic reading of the display data memory.
Page 190: Lcd Controller/Driver Configuration
CHAPTER 16 LCD CONTROLLER/DRIVER 16.2 LCD Controller/Driver Configuration The LCD controller/driver consists of the following hardware. Table 16-2. LCD Controller/Driver Configuration Item Configuration Display outputs Segment signals : 20 Dedicated segment signals: 5 Segment signal/input/output port alternate function: 14 Segment signal/input/output port/16-bit timer prescaler output alternate function: 1 Common signals : 4 (COM0 to COM3) Control registers...
Page 191 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-2. LCD Clock Select Circuit Block Diagram Prescaler LCDCL LCDM6 LCDM5 LCDM4 LCD display mode register Internal bus Remarks 1. LCDCL : LCD clock 2. f : LCD clock frequency...
Page 192: Lcd Controller/Driver Control Registers
CHAPTER 16 LCD CONTROLLER/DRIVER 16.3 LCD Controller/Driver Control Registers The LCD controller/driver is controlled by the following two registers. • LCD display mode register (LCDM) • LCD display control register (LCDC) (1) LCD display mode register (LCDM) This register sets display operation enabling/disabling, the LCD clock, frame frequency. LCDM is set with a 1-bit or 8-bit memory manipulation instruction.
Page 193 CHAPTER 16 LCD CONTROLLER/DRIVER (2) LCD display control register (LCDC) This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input/output port functions. LCDC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDC to 00H.
Page 194: Lcd Controller/Driver Settings
CHAPTER 16 LCD CONTROLLER/DRIVER 16.4 LCD Controller/Driver Settings LCD controller/driver settings should be performed as shown below. <1> Set the initial value in the display data memory (FA59H to FA6CH). <2> Set the pins to be used as segment outputs in the LCD display control register (LCDC). <3>...
Page 195: Lcd Display Data Memory
CHAPTER 16 LCD CONTROLLER/DRIVER 16.5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA59H to FA6CH. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Figure 16-5 shows the relationship between the LCD display data memory contents and the segment outputs/ common outputs.
Page 196: Common Signals And Segment Signals
CHAPTER 16 LCD CONTROLLER/DRIVER 16.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage V ).
Page 197 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-6 shows the common signal waveform, and Figure 16-7 shows the common signal and segment signal voltages and phases. Figure 16-6. Common Signal Waveform COMn (Divided by 4) = 4 x T T: One LCDCL cycle : Frame frequency Figure 16-7.
Page 198: Supplying Lcd Drive Voltage
CHAPTER 16 LCD CONTROLLER/DRIVER 16.7 Supplying LCD Drive Voltage V , and V The µ PD780973 Subseries have a split resistor to create an LCD drive voltage, and the drive voltage is fixed to 1/3 bias. To supply various LCD drive voltages, internal V or external V supply voltage can be selected.
Page 199 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-8. Example of Connection of LCD Drive Power Supply (a) To supply LCD drive voltage from V LIPS P-ch (= 1) Open V (b) To supply LCD drive voltage from external source LIPS P-ch (= 0) 3R •...
Page 200: Display Mode
CHAPTER 16 LCD CONTROLLER/DRIVER 16.8 Display Mode 16.8.1 4-time-division display example Figure 16-10 shows the connection of a 4-time-division type 10-digit LCD panel with the display pattern shown in Figure 16-9 with the µ PD780973 Subseries segment signals (S0 to S19) and common signals (COM0 to COM3). The display example is “1234567890,”...
Page 201 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-10. 4-Time-Division LCD Panel Connection Example COM3 COM2 COM1 COM0 FA6CH FA5FH FA59H...
Page 202 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-11. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM3 +1/3V COM0 to S8 –1/3V –V +1/3V COM1 to S8 –1/3V –V...
Page 203: Cautions On Emulation
CHAPTER 16 LCD CONTROLLER/DRIVER 16.9 Cautions on Emulation (1) LCD timer control register (LCDTM) To perform debugging with an in-circuit emulator (IE-78K0-NS), the LCD timer control register (LCDTM) must be set. LCDTM is a register used to set a probe board (IE-780974-NS-EM1). LCDTM is a write-only register that controls supply of the LCD clock.
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Page 205: Chapter 17 Sound Generator
CHAPTER 17 SOUND GENERATOR 17.1 Sound Generator Function The sound generator has the function to sound the buzzer from an external speaker, and the following two signals are output. (1) Basic cycle output signal (with/without amplitude) The signal is a buzzer signal with a variable frequency. By setting bits 0 to 2 (SGCL0 to SGCL2) of the sound generator control register (SGCR), the signal in a range of 0.25 to 7.7 kHz can be output (when f = 8.38 MHz).
Page 206: Sound Generator Configuration
CHAPTER 17 SOUND GENERATOR Figure 17-2. Concept of Each Signal Basic cycle output SGOF (without amplitude) Amplitude output SGOA Basic cycle output SGO (with amplitude) 17.2 Sound Generator Configuration The sound generator consists of the following hardware. Table 17-1. Sound Generator Configuration Item Configuration 8 bits ×...
Page 207: Sound Generator Control Registers
CHAPTER 17 SOUND GENERATOR 17.3 Sound Generator Control Registers The following three types of registers are used to control the sound generator. • Sound generator control register (SGCR) • Sound generator buzzer control register (SGBR) • Sound generator amplitude register (SGAM) (1) Sound generator control register (SGCR) SGCR is a register which sets up the following four types.
Page 208 CHAPTER 17 SOUND GENERATOR Figure 17-3. Sound Generator Control Register (SGCR) Format Address: FF94H After Reset: 00H Symbol SGCR SGOB SGCL2 SGCL1 SGCL0 Sound Generator Operation Selection Timer operation stopped SGOF/SGO and SGOA for low-level output Sound generator operation SGOF/SGO and SGOA for output Caution Before setting the TCE bit, set all the other bits.
Page 209 CHAPTER 17 SOUND GENERATOR The maximum and minimum values of the buzzer output frequency are as follows. SGCL2 SGCL1 SGCL0 Maximum and Minimum Values of Buzzer Output = 8 MHz = 8.38 MHz Max. (kHz) Min. (kHz) Max. (kHz) Min. (kHz) 3.677 1.953 3.851...
Page 210 CHAPTER 17 SOUND GENERATOR Figure 17-4. Sound Generator Buzzer Control Register (SGBR) Format Address: FF95H After Reset: 00H Symbol SGBR SGBR3 SGBR2 SGBR1 SGBR0 Note Buzzer Output Frequency (kHz) SGBR3 SGBR2 SGBR1 SGBR0 = 8 MHz = 8.38 MHz 3.677 3.851 3.472 3.637...
Page 211 CHAPTER 17 SOUND GENERATOR Figure 17-5. Sound Generator Amplitude Register (SGAM) Format Address: FF96H After Reset: 00H Symbol SGAM SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 Amplitude 0/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128...
Page 212: Sound Generator Operations
CHAPTER 17 SOUND GENERATOR 17.4 Sound Generator Operations 17.4.1 To output basic cycle signal SGOF (without amplitude) Select SGOF output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to “0”. The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output. At the same time, the amplitude signal with an amplitude specified by the SGAM0 to SGAM6 is output from the SGOA pin.
Page 213: Chapter 18 Meter Controller/Driver
CHAPTER 18 METER CONTROLLER/DRIVER 18.1 Meter Controller/Driver Functions The meter controller/driver is a function to drive a stepping motor for external meter control or cross coil. • Can set pulse width with a precision of 8 bits • Can set pulse width with a precision of 8 + 1 bits with 1-bit addition function •...
Page 214: Meter Controller/Driver Configuration
CHAPTER 18 METER CONTROLLER/DRIVER Figure 18-2. 1-Bit Addition Circuit Block Diagram Compare register (MCMPnm) ADBn1 ADBn0 Compare control register (MCMPCn) Internal bus Remark n = 1 to 4, m = 0, 1 18.2 Meter Controller/Driver Configuration The meter controller/driver consists of the following hardware. Table 18-1.
Page 215 CHAPTER 18 METER CONTROLLER/DRIVER (2) Compare register n0 (MCMPn0) MCMPn0 is an 8-bit register that can rewrite compare values through specification of bit 4 (TENn) of the compare control register n (MCMPCn). RESET input sets this register to 00H and clears hardware to 0. MCMPn0 is a register that supports read/write only for 8-bit access instructions.
Page 216: Meter Controller/Driver Control Registers
CHAPTER 18 METER CONTROLLER/DRIVER 18.3 Meter Controller/Driver Control Registers The meter controller/driver is controlled by the following three registers. • Timer mode control register (MCNTC) • Compare control register n (MCMPCn) • Port mode control register (PMC) Remark n = 1 to 4 (1) Timer mode control register (MCNTC) MCNTC is an 8-bit register that controls the operation of the free-running up counter (MCNT).
Page 217 CHAPTER 18 METER CONTROLLER/DRIVER (2) Compare control register (MCMPCn) MCMPCn is an 8-bit register that controls the operation of the compare register and output direction of the PWM pin. MCMPCn is set with an 8-bit memory manipulation instruction. RESET input clears MCMPCn to 00H. Figure 18-4 shows the MCMPCn format.
Page 218 CHAPTER 18 METER CONTROLLER/DRIVER Figure 18-5. Port Mode Control Register (PMC) Format Address: FF6AH After Reset: 00H Symbol MOD4 MOD3 MOD2 MOD1 MOD4 Meter 4 Full/Half Bridge Selection Meter 4 output is full bridge. Meter 4 output is half bridge. MOD3 Meter 3 Full/Half Bridge Selection Meter 3 output is full bridge.
Page 219 CHAPTER 18 METER CONTROLLER/DRIVER The relation among the ENn and MODn bits of the PMC register, DIRn1 and DIRn0 bits of the MCMPCn register, and output pins is shown below. MODn DIRn1 DIRn0 SMn1 SMn2 SMn3 SMn4 Mode (sin+) (sin–) (cos+) (cos–) ×...
Page 220: Meter Controller/Driver Operations
CHAPTER 18 METER CONTROLLER/DRIVER 18.4 Meter Controller/Driver Operations 18.4.1 Basic operation of free-running up counter (MCNT) The free-running up counter is counted up by the count clock selected by the PCS bit of the timer mode control register. The value of MCNT is cleared by RESET input. The counting operation is enabled or disabled by the PCE bit of the timer mode control register (MCNTC).
Page 221: Operation Of 1-Bit Addition Circuit
CHAPTER 18 METER CONTROLLER/DRIVER 18.4.3 Operation of 1-bit addition circuit Figure 18-7. Timing in 1-Bit Addition Circuit Operation MCNT Value OVF (Overflow) Match signal of expected value N PWM output of expected value N (1-bit non-addition) PWM output of expected value N (1-bit addition) PWM output of expected value N+1...
Page 222: Pwm Output Operation (Output With 1 Clock Shifted)
CHAPTER 18 METER CONTROLLER/DRIVER 18.4.4 PWM output operation (output with 1 clock shifted) Figure 18-8. Timing of Output with 1 Clock Shifted Count clock Meter 1 sin (SM11, SM12) Meter 1 cos (SM13, SM14) Meter 2 sin (SM21, SM22) Meter 2 cos (SM23, SM24) Meter 3 sin (SM31, SM32)
Page 223: Chapter 19 Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled state. It does not undergo priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 224 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List Vector Basic Interrupt Source Note 1 Internal/ Interrupt Type Default Table Configuration External Name Trigger Note 2 Priority Address Type Non-maskable — INTWDT Watchdog timer overflow Internal 0004H (with non-maskable interrupt selected) Maskable INTWDT Watchdog timer overflow...
Page 225 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt Priority control Vector table request circuit address generator Standby release signal (B) Internal maskable interrupt Internal bus Priority control Vector table Interrupt circuit address generator...
Page 226 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except 16-bit timer capture input) Internal bus External interrupt edge enable register (EGP, EGN) Priority control Vector table Interrupt Edge circuit address generator request detector Standby release signal (E) Software interrupt...
Page 227: Interrupt Function Control Registers
CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Interrupt Function Control Registers The following 7 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...
Page 228 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 229 CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction.
Page 230 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag registers are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
Page 231 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP2. EGP and EGN are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 232 CHAPTER 19 INTERRUPT FUNCTIONS (5) Prescaler mode register (PRM0) This register specifies the valid edge for TI00/P40 to TI02/P42 pins input. PRM0 is set with an 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 19-6. Prescaler Mode Register (PRM0) Format Address: FF70H After Reset: 00H R/W Symbol PRM0...
Page 233 CHAPTER 19 INTERRUPT FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple processing are mapped.
Page 234: Interrupt Servicing Operations
CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (to 0), and the contents of the vector table are loaded into PC and branched.
Page 235 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending Interrupt...
Page 236 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine Execution of NMI request <1> NMI request <1> NMI request <2> held pending NMI request <2>...
Page 237: Maskable Interrupt Request Acknowledge Operation
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1).
Page 238 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-11. Interrupt Request Acknowledge Processing Algorithm Start ××IF = 1? Yes (Interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority interrupt request among those Any interrupt simultaneously generated request among those...
Page 239: Software Interrupt Request Acknowledge Operation
CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-12. Interrupt Request Acknowledge Timing (Minimum Time) 6 clocks PSW and PC Save, Interrupt servicing CPU processing Instruction Instruction Jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 19-13.
Page 240: Multiple Interrupt Servicing
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Multiple interrupt servicing Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non-maskable interrupts).
Page 241 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-14. Multiple Interrupt Examples (1/2) Example 1. Multiple interrupts occur twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI RETI...
Page 242 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-14. Multiple Interrupt Examples (2/2) Example 3. Multiple interrupt servicing does not occur because interrupt is not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 0 1 instruction execution RETI...
Page 243: Interrupt Request Hold
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
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Page 245: Chapter 20 Standby Function
CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode Halt instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.
Page 246: Standby Function Control Register
CHAPTER 20 STANDBY FUNCTION 20.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 247: Standby Function Operations
CHAPTER 20 STANDBY FUNCTION 20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode setting and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 20-1. HALT Mode Operating Status HALT Mode Setting During HALT Instruction Execution Using Main System Clock Item...
Page 248 CHAPTER 20 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
Page 249 CHAPTER 20 STANDBY FUNCTION (c) Clear upon RESET input As in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 20-3. HALT Mode Clear upon RESET Input Wait HALT instruction : 15.6 ms) RESET signal Reset...
Page 250: Stop Mode
CHAPTER 20 STANDBY FUNCTION 20.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
Page 251 CHAPTER 20 STANDBY FUNCTION (2) STOP mode clear The STOP mode can be cleared with the following two types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 252 CHAPTER 20 STANDBY FUNCTION (b) Clear upon RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 20-5. STOP Mode Clear upon RESET Input Wait STOP instruction : 15.6 ms) RESET signal Reset...
Page 253: Chapter 21 Reset Function
CHAPTER 21 RESET FUNCTION 21.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 254 CHAPTER 21 RESET FUNCTION Figure 21-2. Timing of Reset by RESET Input Oscillation Normal operation Reset period stabilization Normal operation (Reset processing) (Oscillation stop) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 21-3. Timing of Reset due to Watchdog Timer Overflow Oscillation Normal operation Reset period...
Page 255 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General register...
Page 256 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (2/2) Hardware Status After Reset 8-bit timer TM1 to TM3 Timer counters (TM1 to TM3) Compare registers (CR1 to CR3) Clock select registers (TCL1 to TCL3) Mode control registers (TMC1 to TMC3) Watch timer Mode control register (WTM) Watchdog timer...
Page 257: Chapter 22 Μ Pd78F0974
CHAPTER 22 µ PD78F0974 The µ PD78F0974 replace the internal ROM of the µ PD780973(A) with flash memory to which a program can be written, deleted and overwritten while mounted on a board. Table 22-1 lists the differences between the µ PD78F0974 and the µ...
Page 258: Memory Size Switching Register
CHAPTER 22 µ PD78F0974 22.1 Memory Size Switching Register The µ PD78F0974 allow users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of the µ PD780973(A) with a different size of internal memory capacity can be achieved.
Page 259: Flash Memory Programming
CHAPTER 22 µ PD78F0974 22.2 Flash Memory Programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash writer (Flashpro II) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II.
Page 260: Flash Memory Programming Function
CHAPTER 22 µ PD78F0974 22.2.2 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 22-4. Table 22-4. Main Functions of Flash Memory Programming Function Description Reset...
Page 261 CHAPTER 22 µ PD78F0974 Figure 22-4. Flashpro II Connection Using UART Method µ Flashpro II PD78F0974 RESET RESET Figure 22-5. Flashpro II Connection Using Pseudo 3-Wire Serial I/O Method µ Flashpro II PD78F0974 RESET RESET P05, P95 (Serial clock input) P07, P97 (Serial data input) P06, P96 (Serial data output)
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Page 263: Chapter 23 Instruction Set
CHAPTER 23 INSTRUCTION SET This chapter lists the instruction set of the µ PD780973 Subseries. For details of the operation and machine language (instruction code), refer to the separate document “78K/0 Series User’s Manual—Instructions (U12326E).”...
Page 264: Legend For Operation List
CHAPTER 23 INSTRUCTION SET 23.1 Legend for Operation List 23.1.1 Operand identifiers and description formats Operands are described in “Operand” column of each instruction in accordance with the description format of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description formats, select one of them.
Page 265: Description Of "Operation" Column
CHAPTER 23 INSTRUCTION SET 23.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 266: Operation List
CHAPTER 23 INSTRUCTION SET 23.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 r ← byte r, #byte – (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte – A ← r Note 3 A, r –...
Page 267 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 rp ← word rp, #word – (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word – AX ← (saddrp) AX, saddrp (saddrp) ←...
Page 268 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A, CY ← A – byte × × × A, #byte – (saddr), CY ← (saddr) – byte × × × saddr, #byte A, CY ←...
Page 269 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A ← A byte × A, #byte – (saddr) ← (saddr) byte × saddr, #byte A ← A r × Note 3 A, r –...
Page 270 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 AX, CY ← AX + word × × × ADDW AX, #word – 16-bit AX, CY ← AX – word × ×...
Page 271 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) × CY, saddr.bit CY ← CY sfr.bit × CY, sfr.bit – CY ← CY A.bit × AND1 CY, A.bit –...
Page 272 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 273 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 saddr.bit, $addr16 PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 274: Instructions Listed By Addressing Type
CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
Page 275 CHAPTER 23 INSTRUCTION SET Second Operand [HL + byte] Note #byte saddr !addr16 PSW [DE] [HL] $addr16 None [HL + B] First Operand [HL + C] MOV MOV MOV MOV MOV MOV MOV MOV ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC...
Page 276 CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None 1st Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 277 CHAPTER 23 INSTRUCTION SET (4) Call/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP...
Page 278 [MEMO]...
Page 279: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD780973 Subseries. Figure A-1 shows the development tool configuration.
Page 280 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tools • System simulator • Integrated debugger •...
Page 281 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tools • System simulator • Integrated debugger •...
Page 282: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K/0 This assembler converts programs written in mnemonics into an object code Assembler Package executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler is used in combination with an optional device file (DF780974).
Page 283: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS µ S××××RA78K0 µ S××××CC78K0 µ S××××DF780974 µ S××××CC78K0-L ×××× Host Machine Supply Medium AA13 PC-9800 Series Windows 3.5-inch 2HD FD Notes 1, 2 Japanese version AB13 IBM PC/AT™ and compatibles Windows 3.5-inch 2HC FD Notes 1, 2 Japanese version BB13 Windows...
Page 284: Debugging Tools
APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS Note IE-78K0-NS This in-circuit emulator is used to debug hardware and software when developing application In-circuit Emulator systems using the 78K/0 Series. It supports the integrated debugger (ID78K0-NS). This emulator is used in combination with a power unit, an emulation probe, and an interface adapter for connection to a host machine.
Page 285 APPENDIX A DEVELOPMENT TOOLS A.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A Note IE-78001-R-A This in-circuit emulator is used to debug hardware and software when developing In-circuit Emulator application systems using the 78K/0 Series. It supports the integrated debugger (ID78K0).
Page 286: Software
APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (1/2) SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine. The SM78K0 operates on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
Page 287 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (2/2) Note ID78K0-NS This is a control program used to debug the 78K/0 Series. The graphical user interfaces employed are Windows for personal computers and OSF/ Integrated Debugger (Supports in-circuit emulator Motif for EWSs, offering the standard appearance and operability typical of these IE-78K0-NS) interfaces.
Page 288: Upgrading Former In-Circuit Emulator For 78K/0 Series To Ie-78001-R-A
IE-78001-R-A in-circuit emulator by simply replacing the break board with the IE-78001-R-BK (under development). Table A-1. Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A Note In-circuit Emulator Cabinet Upgrading Board to be Purchased IE-78000-R Required IE-78001-R-BK IE-78000-R-A Not required Note To upgrade your cabinet, bring it to NEC.
Page 289 APPENDIX A DEVELOPMENT TOOLS Dimensions of Conversion Adapter (TGF-080RAP) Figure A-2. Dimensions of TGF-080RAP (Reference) H G F E M N O X W U Protrusion height ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 20.65 0.813 20.65 0.813 14.1 0.555 14.40 0.567 0.8x15=12 0.031x0.591=0.472...
Page 290 [MEMO]...
Page 291: Appendix B Embedded Software
APPENDIX B EMBEDDED SOFTWARE For efficient development and maintenance of the µ PD780973 Subseries, the following embedded software products are available. Real-Time OS (1/2) RX78K/0 is a real-time OS conforming with the µ ITRON specifications. RX78K/0 Real-time OS Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied.
Page 292 APPENDIX B EMBEDDED SOFTWARE Real-Time OS (2/2) µ lTRON specification subset OS. Nucleus of MX78K0 is supplied. MX78K0 This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next.
Page 293: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Name) A/D conversion result register (ADCR1) … 150 A/D converter mode register (ADM1) … 152 Analog input channel specification register (ADS1) … 153 Asynchronous serial interface mode register (ASIM) … 167, 171, 172 Asynchronous serial interface status register (ASIS) …...
Page 294 APPENDIX C REGISTER INDEX External interrupt falling edge enable register (EGN) … 231 External interrupt rising edge enable register (EGP) … 231 Interrupt mask flag register 0H (MK0H) … 229 Interrupt mask flag register 0L (MK0L) … 229 Interrupt mask flag register 1L (MK1L) … 229 Interrupt request flag register 0H (IF0H) …...
Page 295 APPENDIX C REGISTER INDEX Receive buffer register (RXB) … 166 Serial I/O shift register (SIO) … 184 Serial operation mode register (CSIM) … 185, 186 16-bit timer mode control register (TMC0) … 103 16-bit timer register (TM0) … 102 Sound generator amplitude register (SGAM) … 210 Sound generator buzzer control register (SGBR) …...
Page 296: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR1 A/D conversion result register … 150 ADM1 A/D converter mode register … 152 ADS1 Analog input channel specification register … 153 ASIM Asynchronous serial interface mode register … 167, 171, 172 ASIS Asynchronous serial interface status register …...
Page 297 APPENDIX C REGISTER INDEX MCMP40 : Compare register 40 … 215 MCMP41 : Compare register 41 … 215 MCMPC1 : Compare control register 1 … 217 MCMPC2 : Compare control register 2 … 217 MCMPC3 : Compare control register 3 … 217 MCMPC4 : Compare control register 4 …...
Page 298 APPENDIX C REGISTER INDEX SGCR Sound generator control register … 207 Serial I/O shift register … 184 TCL1 Timer clock select register 1 … 113 TCL2 Timer clock select register 2 … 122 TCL3 Timer clock select register 3 … 122 16-bit timer register …...
Page 299: Appendix D Revision History
APPENDIX D REVISION HISTORY The revision history of this edition is listed below. “Chapter” indicates the chapter of the previous edition where the revision was made. (1/2) Edition Revisions Chapter Second Table 2-1. Pin Input/Output Circuit Types CHAPTER 2 PIN FUNCTION Correction of ports 8 and 9 input/output circuit types Figure 2-1.
Page 300 APPENDIX D REVISION HISTORY (2/2) Edition Revisions Chapter Second 17.1 Sound Generator Function CHAPTER 17 Correction of description on (1) Basic cycle output signal SOUND GENERATOR (with/without amplitude) 18.2 Meter Controller/Driver Configuration CHAPTER 18 Addition of Cautions to (1) Free running up counter (MCNT) METER CONTROLLER/DRIVER Table 20-1.
Page 301 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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Mpd780973a Mpd780974

NEC mPD780973 Series Preliminary User's Manual

Chapter 1 Outline

Chapter 3 Cpu Architecture

Chapter 4 Eeprom

Chapter 5 Port Functions

Chapter 6 Clock Generator

Chapter 7 16-Bit Timer 0 Tm0

Chapter 8 8-Bit Timer 1 Tm1

Chapter 9 8-Bit Timer/Event Counters 2, 3 Tm2, Tm3

Chapter 10 Watch Timer

Chapter 11 Watchdog Timer

Chapter 12 Clock Output Control Circuit

Chapter 13 A/D Converter

Chapter 14 Serial Interface Uart

Chapter 15 Serial Interface Sio3

Chapter 16 Lcd Controller/Driver

Chapter 17 Sound Generator

Chapter 18 Meter Controller/Driver

Chapter 19 Interrupt Functions

Chapter 20 Standby Function

Chapter 21 Reset Function

CHAPTER 22 Μ PD78F0974

Chapter 23 Instruction Set

Appendix A Development Tools

Appendix B Embedded Software

Appendix C Register Index

Appendix D Revision History

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Summary of Contents for NEC mPD780973 Series