Yamaha ICP1 Service Manual page 9

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HD6417727F160C (X2890B00) CPU
PIN
NAME
NO.
1 Vcc-RTC
XTAL2
2
3 EXTAL2
Vss-RTC
4
MD1
5
6 MD2
NMI
7
8 IRQ0/IRL0_/PTH[0]
IRQ1/IRL1_/PTH[1]
9
10 IRQ2/IRL2_/PTH[2]
IRQ3/IRL3_/PTH[3]
11
IRQ4/PTH[4]
12
13 VEPWC
VCPWC
14
15 MD5
/BREQ
16
17 /BACK
18 VssQ
CKIO2
19
20 VccQ
D31/PTB[7]
21
22 D30/PTB[6]
D29/PTB[5]
23
24 D28/PTB[4]
25 D27/PTB[3]
D26/PTB[2]
26
27 D25/PTB[1]
D24/PTB[0]
28
29 VssQ
D23/PTA[7]
30
VccQ
31
32 D22/PTA[6]
D21/PTA[5]
33
34 D20/PTA[4]
Vss
35
36 D19/PTA[3]
Vcc
37
D18/PTA[2]
38
39 D17/PTA[1]
D16/PTA[0]
40
41 D15
VssQ
42
43 D14
VccQ
44
D13
45
46 D12
D11
47
48 D10
D9
49
50 D8
51 D7
D6
52
53 VssQ
TE
L 13942296513
D5
54
55 VccQ
D4
56
57 D3
58 D2
D1
59
60 D0
A0
61
62 A1
A2
63
VssQ
64
65 A3
VccQ
66
67 A4
A5
68
69 A6
A7
70
A8
71
72 A9
A10
73
74 A11
VssQ
75
76 A12
77 VccQ
A13
78
79 A14
A15
80
81 A16
A17
82
83 A18
84 A19
A20
85
86 VssQ
A21
87
88 VccQ
A22
89
A23
90
91 Vss
A24
92
93 Vcc
A25
94
95 BS_/PTK[4]
RD_
96
WE0_/DQMLL
97
98 WE1_/DQMLU/WE
WE2_/DQMUL/ICIORD_/PTK[6]
99
100 VssQ
WE3_/DQMUU/ICIOWR_/PTK{7}
101
102 VccQ
RD/WR_
103
PTE[7]/PCC0RDY/AUDSYNC_
104
105 /CS0
www
/CS2
106
107 /CS3
/CS4/PTK[2]
108
109 /CS5/CE1A_/PTK[3}
110 /CS6/CE1B_
CE2A_/PTE[4]
111
112 CE2B_/PTE[5]
AFE_HC1/USB1d_DPLS/PTK[0]
113
.
114 AFE_RLYCNT_/USB1d_DMNS/PTK[1]
VssQ
115
116 AFE_SCLK/USB1d_TXDPLS
117 VccQ
PTM[7]/PTINT[7]/AFE_FS/USB1d_RCV
118
119 PTM[6]/PTINT[6]/AFE_RXIN/USB1d_SPEED
PTM[5]/PTINT[5]/AFE_TXOUT/USB1d_TXSE0
120
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I/O FUNCTION
- Power supply for RTC (1.9V)
-
Not in use (XTAL for internal RTC)
-
- Power supply for RTC (0V)
-
Clock mode setting
-
-
Not in use (Non-maskable interrupt request)
I
I
I
External interrupt request
I
I
O VEE control pin for LCD panel
-
VCC control pin for LCD panel
-
Big endian setting
- Not in use (bus request)
-
Bus acknowledge
- VssQ
-
System clock output
- VccQ
I/O
I/O
I/O
I/O
Data bus
I/O
I/O
I/O
I/O
-
VssQ
I/O Data bus
-
VccQ
I/O
I/O
Data bus
I/O
- Vss
I/O
Data bus
- Vcc
I/O
I/O
Data bus
I/O
-
- VssQ
-
Data bus
- VccQ
-
-
-
-
Data bus
-
-
-
-
- VssQ
- Data bus
-
VccQ
-
-
- Data bus
-
-
-
-
Address bus
-
-
VssQ
- Address bus
-
VccQ
-
-
-
-
Address bus
-
-
-
-
- VssQ
-
Address bus
- VccQ
-
-
-
-
Address bus
-
-
-
-
- VssQ
- Address bus
-
VccQ
-
Address bus
-
- Vss
-
Address bus
-
Vcc
- Address bus
O
Not connected (bus cycle start signal)
- Read strobe
O
Write 0 signal
O Write 1 signal
O
Write 2 signal
-
VssQ
O Write 3 signal
-
VccQ
O Read/Write
O
I/O
- Chip Select 0
-
Chip Select 2
-
Chip Select 3
O Chip Select 4
O
x ao Chip Select 5 u163
y
O Chip Select 6
O
Output port (SWP50 Reset)
O Output port (PLG Board Reset)
O SPD DATA
i
O
SPD CL
- VssQ
I
Not in use (USB1 D+ transmission)
- VccQ
I
I Not in use
I
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8
PIN
NAME
NO.
121 PTM[4]/PINT[4]/AFE_RDET_/USB1d_TXDMNS
Reserved/USB1d_SUSPEND
122
123 USB1_ovr_crnt/USBF_VBUS
USB2_ovr_crnt_
124
125 RTS2_/USB1d_TXENL
PTE[2]/USB1_pwr_en
126
127 PTE[1]/USB2_pwr_en
128 CKE/PTK[5]
/RAS3/PTJ[0]
129
130 Reserved/PTJ[1]
Reserved//CAS/PTJ[2]
131
132 VssQ
Reserved/PTJ[3]
133
VccQ
134
135 Reserved/PTJ[4]
Reserved/PTJ[5]
136
137 Vss
PTD[5]/CL1
138
139 Vcc
PTD[7]/DON
140
PTE[6]/M_DISP
141
142 PTE[3]/FLM
PTE[0]/TDO
143
144 PCC0RESET/DRACK0
PCC0DRV_/DACK0_
145
146 /WAIT
/RESETM
147
/ADTRG/PTH[5]
148
149 /IOIS16/PTG[7]
/ASEMD0
150
151 PTG[5]/ASEBRKAK_
PTG[4]
152
153 PCC0BVD2/PTG[3]/AUDATA[3]
154 PCC0BVD1/PTG[2]/AUDATA[2]
Vss
155
156 PCC0CD2/PTG[1]/AUDATA[1]
Vcc
157
158 PCC0CD1/PTG[0]/AUDATA[0]
VssQ
159
160 PTF[7]/PINT[15]/TRST_
161 VccQ
PTF[6]/PINT[14]/TMS
162
163 PTF[5]/PINT[13]/TDI
PTF[4]/PINT[12]/TCK
164
165 PTF[3]/PINT[11]/Reserved
PCCREG_/PTF[2]/Reserved
166
PCC0VS1_/PTF[1]/Reserved
167
168 PCC0VS2_/PTF[0]/Reserved
MD0
169
170 Vcc-PLL1
CAP1
171
172 Vss-PLL1
Q Q
Vss-PLL2
173
3 6 7 1 3 1 5
CAP2
174
175 Vcc-PLL2
PCC0WAIT_/PTH[6]/AUDCK
176
177 Vss
Vcc
178
179 XTAL
180 EXTAL
LCD15/PTM[3]/PINT[10]
181
182 LCD14/PTM[2]/PINT[9]
LCD13/PTM[1]/PINT[8]
183
184 LCD12/PTM[0]
STATUS0/PTJ[6]
185
186 STATUS1/PTJ[7]
187 CL2/PTH[7]
VssQ
188
189 CKIO
VccQ
190
191 TxD0/SCPT[0]
SCK0/SCPT[1]
192
193 TxD_SIO/SCPT[2]
194 SIOMCLK/SCPT[3]
TxD2/SCPT[4]
195
196 SCK_SIO/SCPT[5]
SIOFSYNC/SCPT[6]
197
198 RxD0/SCPT[0]
RxD_SIO/SCPT[2]
199
Vss
200
201 RxD2/SCPT[4]
Vcc
202
203 SCPT[7]/CTS2_/IRQ5
LCD11/PTC[7]/PINT[3]
204
205 LCD10/PTC[6]/PINT[2]
LCD9/PTC[5]/PINT[1]
206
VssQ
207
208 LCD8/PTC[4]/PINT[0]
VccQ
209
210 LCD7/PTD[3]
LCD6/PTD[2]
211
212 LCD5/PTC[3]
213 LCD4/PTC[2]
LCD3/PTC[1]
214
215 LCD2/PTC[0]
LCD1/PTD[1]
216
217 LCD0/PTD[0]
DREQ0_/PTD[4]
218
219 LCK/UCLK/PTD[6]
220 /RESETP
CA
221
222 MD3
MD4
223
224 /Scan_testen
Avcc_USB
225
USB1_P
226
227 USB1_M
Avss_USB
228
229 USB2_P
co
USB2_M
230
231 Avcc_USB
Avss
232
AN[2]/PTL[2]
233
.
234 AN[3]/PTL[3]
AN[4]/PTL[4]
235
236 AN[5]/PTL[5]
Avcc
237
238 AN[6]/PTL[6]/DA[1]
239 AN[7]/PTL[7]/DA[0]
Avss
240
9 4 2 8
DM: IC104
DM2-EL: IC006
I/O FUNCTION
I
Not in use
O
I USB function VBUS
- USB2_HOST2 over current detection
O Not in use
O USB1 voltage control
O USB2 voltage control
O Enable (SDRAM)
O RAS for SDRAM
O Not in use
O CAS for SDRAM
- VssQ
O Output port (DAC Reset)
- VccQ
O Output port (SIO Reset)
O Output port (DAC Mute)
- Vss
O LCD line clock
- Vcc
O LCD DISPLAY ON
O LCD alternater
O LCD frame line marker
O JTAG (test data output)
O DMA request acceptance
O DMA acknowledge
- Hardware wait request
- Manual reset request
I Analog A/D trigger
I
-
Not in use
I
I
I
- Vss
I Not in use
- Vcc
I Not in use
- VssQ
I
Not in use
- VccQ
I
I
I
I Not in use
I
I
I
- Clock mode setting
- Power supply for Vcc_PLL1 - PLL1(1.9V)
- External capacitance for CAP1 _ PLL1
- Power supply for Vss_PLL1 _ PLL1(0V)
- Power supply for Vss_PLL2 _ PLL2 (0V)
0 5 8 2 9 9 4 2 8
- External capacitance for CAP2 _ PLL2
- Power supply for Vcc_PLL2 _ PLL2 (1.9V)
I Not in use
- Vss
- Vcc
- Clock oscillator
- External clock
I
I Not in use
I
I Input port (Flash ROM RY/BY)
O Output port (Flash ROM write protect)
O Output port (Flash ROM ACC)
O LCD clock output
- VssQ
- System clock input/output (for SDRAM)
- VccQ
O Output port for SCI
O
O Not in use
O
O Output port for SCI
O
Not in use
O
i Receiving data 0
i Not in use
- Vss
i Receiving data 2
- Vcc
I Not in use
O Output port (PLG CLOCK ON/OFF)
O
Not in use
O
- VssQ
O Not in use
- VccQ
O LCD DATA7
O LCD DATA6
O LCD DATA5
O LCD DATA4
O LCD DATA3
O LCD DATA2
O LCD DATA1
O LCD DATA0
I DMA request
I
USB clock
- Power on reset request
- Hardware standby request
-
Bus width setting for area0
-
- Test pin (fixed to 3.3V)
- USB analog power supply (3.3V)
m
IO USB1 data input/output (+)
IO USB1 data input/output (-)
- USB analog power supply (0V)
IO USB2 data input/output (+)
IO USB2 data input/output (-)
- USB analog power supply (3.3V)
- A/D analog power supply (0V)
I
I
AD converter input
I
I
- A/D analog power supply (3.3V)
I AD converter input
O DA converter output (LCD contrast)
- A/D analog power supply (0V)
ICP1
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