Motorola M68HC08 Reference Manual page 106

Software Design
5.6.4 Timers
5.6.4.1 Timer 1
5.6.4.2 Timer 2
Designer Reference Manual
106
Freescale Semiconductor, Inc.
Timer 1 and timer 2 are implemented using MC68HC08MR32 timers.
Timer 3 is a software virtual timer using time base of timer 1.
Timer 1 is provided by timer A channel 1 set in output compare mode. In
this mode the registers TACH1H and TACH1L are used for setting the
output compare value, T1.
• TACNTH and TACNTL form a 16-bit timer A counter with an
infinite counting 16-bit roll over.
• The timer A channel 1 interrupt is called whenever TACH1H =
TACNTH and TACH1L = TACNTL. With each interrupt, the
registers TACH1H and TACH1L are loaded with the new value, T1
= T1+PER_CS_T1, where T1+PER_CS_T1 is a 16-bit addition
with no saturation. So, the constant interrupt period PER_CS_T1
of the timer T1 interrupts is generated.
• The timer unit UNIT_PERIOD_T1_US of timer A is determined by
the MCU bus frequency (8 MHz with a 4-MHz oscillator and
default software setting) and timer prescaler set in TASC. So, the
default software value is 2 s. The timer 1 interrupt function is
provided by the TIMACh1_Int () function.
Timer 2 is provided by timer A channel 3 set in output compare mode. In
this mode, the registers TACH3H and TACH3L are used for setting the
output compare value, T2.
• TACNTH and TACNTL form a 16-bit timer A counter, with infinite
counting 16-bit roll over.
• The actual time is sensed from TACNTH and TACNTL base (e.g.,
time of the commutation, T_Cmt).
• The timer A channel 3 (timer 2) interrupt is called whenever
TACH3H = TACNTH and TACH3L = TACNTL. So, the registers
TACH3H and TACH3L are loaded with the T2 variable value.
Software Design
For More Information On This Product,
Go to: www.freescale.com
DRM028 — Rev 0
MOTOROLA