LG 32LW5700 Manual page 85

Block Diagram
Block Diagram
ISDB-T/S
1400Yen
(HST-J222DHT)
5V
Hitachi Tuner
3.3V
LNB 16V
MP1593
REAR AV
Rear CVBS_OUT (debug)
D-sub RGB
Audio L/R (for RGB)
JACK PACK
JACK PACK
at REAR at REAR
Digital Audio (Optic)
RS-232C (Ctrl./SVC)
10.000MHz
32.768kHz
USB /DVR Ready
JACK PACK JACK PACK
at SIDE
at SIDE
Side CVBS (Gender)
Copyright ⓒ 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
PSK, OFDM AGC
PSK1 I/Q
PSK2 I/Q
TC90522XBG
OFDM1 N/P I2C_0(0x?)
TOSHIBA DEMOD
OFDM2 N/P
SCL/SDA, OFDM/PSK
X-tal I2C_0 SCL/SDA
3.3V 1.2V
16.000Mhz
24V
TX,RX
TX,RX
SI2404
SI3010
MODEM
X-tal
4.9152MHz
CVBS_L/R + D5_L/R
Y Pb Pr, L/R
D5(1080P)
RGB/H/V
Audio L/R
HDMI 1
4x1
HDMI Switch
HDMI 2
TDA19997
I2C_1(0xC0)
HDMI 3
SPDIF
MAX3232
Ethernet Connect
X-tal
MICOM
(uPD78F0513)
X-tal
I2C_2(0x52)
HDMI4
DP/DM/ +5V
USB
L/R
TPA6132
HP Phone JACK
AMP
1.2V 2.5V 3.3V
RESET
PSK1 CLK,DATA,SYNC
PSK2 CLK,DATA,SYNC
OFDM1 CLK,DATA,SYNC
OFDM2 CLK,DATA,SYNC
UART
CTS,RTS,DCD,ESC,INT
RESET
BCM3558
3.3V
Main SOC
400Mhz
32bit
MIPS Dual
2HDMI (1)
4CVBS INPUT(1)
3.3/5V 3SVIDEO INPUT(0)
1RGB(1)
2USB(2)
RX/TX
SCL, SDA_3.3V
3.5V
HP DIFF L/R
3.3V
W25X20BVSNIG
Serial Flash
X-tal
SPI CLK/DATA
24.000Mhz
RESET
I2C
LGE7303C
URSA5
LVDS 60Hz
I2C_1(0xB4)
L/R_SYNC
ADD[0-12], DQ[0-7]
3.3/1.5/1.26V
DDR3 (1Gbit)
DDR_D0[0:15], DQS, DM ...
DDR2 (1Gbit)
DDR2 (1Gbit)
Addr.[ 0:13], ctrl. Data
DDR2 (1Gbit)
DDR_D1[0:15], DQS, DM ...
DDR2 (1Gbit)
Data [0 ... 7]
NAND Flash
(4Gb)
RST,VCC,RES RST,SW
TDA8024
B-CAS Slot
B-CAS
I/O, CLK
I/O, CLK
IC
3.3V 5V
Digital AMP
I2S
NTP7000
I2C_2(0x54)
54MHz
X-tal
24V 3.3V 1.8V
54.000MHz
NVRAM
SCL, SDA_3.3V
I2C_3(0xA8)
3.3V
LGE Confidential
41p
3.3V
LVDS 120Hz
LVDS 120Hz
1.5V
51p
LGE Internal Use Only