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DX-SX1H
IC901 VHiCXD2751Q-1: SACD Playback Signal Processor (CXD2751Q) (1/2)
Pin No. Terminal Name Input/Output
1
XSRQ
2
XSHD
3
VDD
4
VSS
5
SDCK
6
SMUTE
7
XMSLAT
8
MSCK
9
MSDATI
10
MSDATO
11
MSREDY
12*
XMSDOE
13
XRST
14
MCKI
15
VSS
16
CK75S
17
EXCKO1
18*
EXCKO2
19*
LRCK
20*
NC
21*
MNT2
22
TRST
23
TCK
24*
TDI
25*
TENA1
26*
TDO
27
VST
28
VDD
29
VSS
30*, 31* MNT1, MNT0
32*
XBIT
33*
F75HZ
34*
SUPDAT
35*
XSUPAK
36*
SUPEN
37
TEST1
38
VSS
39
TEST2
40, 41
VSS
42*
BCKD
43*-45* NC
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Output
Output terminal for data request to be input in the front end processor.
Input
Input terminal for header flag to be output from the front end processor.
—
Power supply terminal, +3.3V
—
Ground terminal
Input
Input terminal for data transmitting clock to be output from the front end processor
Input
Soft mute terminal
H: Soft mute of audio output, L: Released
Input
Latch input terminal for microcomputer serial communication
Latches addresses and data when this terminal rises.
Input
Shift clock input terminal for microcomputer serial communication
Inputs and shifts the serial input data when the clock to be input in this terminal rises.
Read-out data change when the clock to be input in this terminal falls.
Input
Data input terminal for microcomputer serial communication (Microcomputer -> CXD2751Q)
Inputs serial data and addresses for communication.
Output
Data input terminal for microcomputer serial communication (CXD2751Q -> Microcomputer)
High impedance except during output
Output
Ready-to-output flag for microcomputer serial communication. Outputs "L", if complete.
Open drain.
Output
Data enable terminal for microcomputer serial communication
Makes this terminal active when using the try state buffer outside.
Input
Resets entire IC when reset terminal is "L".
Clock which is output from output terminals EXCKO1, EXCKO2, and LRCK does not stop during reset.
Input
Master clock input terminal
Inputs clock of 512Fs (22.579 MHz) or 768Fs (33.869 MHz).
—
Ground terminal
Input
Master clock select terminal. Selects "H" in case of 768Fs and "L" in case of 512Fs.
Output
External output clock terminal 1. Outputs 768Fs/512Fs/256Fs/128Fs according to setting.
Output
External output clock terminal 2. Outputs 768Fs/512Fs/256Fs/128Fs according to setting.
Input/Output
IFs (44.1kHz) clock input/output terminal. Selects master/slave according to setting.
—
Not used
Output
Monitor output terminal. Outputs partial internal operation according to setting.
Input
Reset terminal for test. Inputs power-on reset signal or fixed at "L".
Input
Test clock input terminal. Fixed at "L".
Input
Test input terminal. Open
Input
Test input terminal. Open
Output
Test input terminal. Open
—
Test ground terminal. Connected to ground
—
Power supply terminal, +3.3V
—
Ground terminal
Output
Monitor output terminal. Outputs partial internal operation according to setting.
Output
DST related monitor terminal. Not connected.
Output
75Hz clock output terminal
Output
Supplementary data serial output terminal
Output
Supplementary data effective flag terminal
Outputs "L" when supplementary data are effective.
Output
Supplementary data byte-unit enable output terminal
Changes to "H" at the break of 1 byte (8 bits) of serial data.
Input
Test input terminal. Fixed at "L".
—
Ground terminal
Input
Test input terminal. Fixed at "L".
—
Ground terminal
Input/Output
Phase reference signal input/output terminal for DSD data phase modulation output
Input/output according to setting
—
Not used
Function
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