Yamaha YSP-1000 Service Manual page 62

A B C
YSP-1000
SCHEMATIC DIAGRAM (DSP 2/3)
1
2
Page 61 B3
3
to DSP_CB1
4
5
6
7
8
9
10
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
62
D E F
3.1
3.3
0
3.3
1.3
0
3.3
3.3
3.3
3.3
0
1.3
1.7
0
1.3
0
1.7
1.7
0.8
1.6
1.7
1.3
0
1.3
0
1.6
1.3
0
DSP2
0
1.3
3.3
0
1.3
3.3
3.3
1.3
3.3
0
1.3
3.3
0
0
1.3
1.3
0
G H I
3.2
0.1
1.3
0
0.7
1.3
1.3
0
3.3
1.7
1.7
3.3
0.5
0
1.3
3.0
3.0
3.0
3.0
3.0
3.0
3.3
0
1.3
3.1
3.1 3.3 0
3.0 3.0 3.0
3.2 3.3 0
3.0
3.0
2.9 3.0 2.9
2.9
0 3.3
1.3 3.0 2.9
0 3.0 2.9
3.3 3.3 0
3.1 3.0 3.2
3.0
3.0 3.0
2.9 0 3.3
3.1 3.1 3.1
0 3.3 0
3.1 3.3
3.3
3.1
0 3.3 1.7
1.3
3.3
3.3
0 0
0 0
0 0
0 1.6
3.2 1.2
3.2 3.1
3.2 3.1
3.3 0
DRAM
J K L
IC12: D60YA003BPYP225
Decoder
EMIF32
McASP1
McASP0
McBSP1
McBSP0
I2C1 Enhanced
DMA
Controller
I2C0
(16 channel)
Timer 1
Timer 0
GP1
GP0
HPI16
IC13: SN74AHC1G08DCKR
2-Input And Gate
A 1 5 Vcc
B 2
GND 3 4 Y
IC16: W9864G6EH-7
1M x 4 Banks x 16 Bits SDRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
WE
A10
MODE
A0
REGISTER
A9
A11
BS0
BS1
REFRESH COLUMN
COUNTER COUNTER
0 0
0 3.3 IC17: MBM29LV160BE-70TN
0 0
16M-bit, 3.0 V-only Flash memory
0 3.0
0 3.1
0 3.1
V
0 3.0 CC RY/BY
0 2.9 V Buffer
SS
0 3.0
2.9
3.3 3.0
3.1 3.3
2.9
3.1 WE
3.2 State
BYTE
Control
0 3.0
0 3.0 RESET
1.6 3.0
Command
1.2 3.1
Register
3.1 3.0
3.1 3.3
3.2 0
3.2 3.3
CE
3.2 0
OE
FLASH
Low V CC Detector
DSP
A to A
0 19
A
-1
M N
Digital Signal Processors
L2 Cache/
L1P Cache
Memory
4 Banks Direct Mapped
64K Bytes 4K Bytes Total
Total
(4-Way)
C67x TM CPU
Instruction Fetch Control
Registers
Instruction Dispatch
Control
L2 Instruction Decode Logic
Memory
Data Path A Data Path B Test
DA610:
A Register File B Register File
192K Bytes In-Circuit
Emulation
DA601:
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t Interrupt
Control
L1D Cache
2-Way Set
R2 ROM
Associative
512K
4K Bytes Total
Bytes
Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #0 BANK #1
SENSE AMPLIFIER SENSE AMPLIFIER
DQ0
DATA CONTROL DQ
CIRCUIT BUFFER
DQ15
UDQM
LDQM
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER SENSE AMPLIFIER
DQ 0 to DQ 15
RY/BY
Erase Voltage Input/Output
Generator Buffer
Program Voltage
Generator STB
Chip Enable
Data Latch
Output Enable
Logic
Y-Decoder Y-Gating
STB
Timer for Address
Program/Erase
Latch
X-Decoder
Cell Matrix