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Sony SS-HQ1 Application Notes

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- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
SS-HQ1 Application Notes
Sony Corporation
Semiconductor Solutions Network Company
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  • Page 1 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 SS-HQ1 Application Notes Sony Corporation Semiconductor Solutions Network Company...

  • Page 2: Table Of Contents

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 CONTENTS System Concept ............................1 1.1. Comparison of SS-HQ1 and SS-1M System Specifications ..............1 1.2. New Functions in SS-HQ1 System ......................2 System Configuration ..........................3 2.1. IC Configuration............................3 2.2. Clock Configuration ..........................5 2.2.1.
  • Page 3 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.9.3. Circuit Configuration for Composite Output ..................29 3.10. Optical Filters ............................. 30 3.10.1. Outline ............................30 Parameter Configuration ........................31 4.1. Communication Parameter Concept...................... 31 4.1.1. Communication Category Concept....................31 4.1.2.
  • Page 4 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 9.1.5. Serial Communication Prohibited Period ..................62 9.1.6. Important Note Regarding Communication ..................62 9.1.7. When Communication is Not Used....................62 9.2. Communication with Peripheral ICs....................... 63 9.2.1. Connection of Communication Bus between DSP (CXD3172AR) and Peripheral ICs ....63 9.2.2.
  • Page 5 Parameter Settings for Each Output Type................. 182 12.1.6. ITU-REC656 ..........................183 12.2. Using external synchronization ......................188 12.2.1. Synchronization for the SS-HQ1 system................... 188 12.2.2. Parameters used to set external synchronization ..............189 12.2.3. Internal mode (INT)........................192 12.2.4. Line lock mode (LL) ........................195 12.2.5.
  • Page 6 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.7. Using the Internal SYNCSEP....................212 12.2.8. VS Lock Mode (VSL-S)......................213 12.2.9. VS Lock Mode (VSL-D)......................215 12.2.10. VBS Lock Mode (VBSLHP)....................... 217 12.2.11. VBS Lock Mode (VBSLHR) ...................... 220 12.2.12.

  • Page 7: System Concept

    The SS-HQ1 system processes camera signals using a two-chip configuration consisting of a DSP (CXD3172AR) and a digital CCD camera head amp (CXA2096N). The following table summarizes the major differences between the SS-HQ1 and the specifications for our SS-1M system, in which CXD2163BR is used as the DSP.

  • Page 8: New Functions In Ss-Hq1 System

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 1.2. New Functions in SS-HQ1 System The SS-HQ1 system contains the new functions listed in the following table. Table 1.2-1 New Functions in SS-HQ1 System New function Basic description Detailed description...

  • Page 9: System Configuration

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 2. System Configuration 2.1. IC Configuration The SS-HQ1 is the digital signal processing system for single CCD color camera. The main LSIs are shown in Table 2.1-1. Table 2.1-1 Main LSIs Main LSIs...
  • Page 10 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 In SS-HQ1, 3ch EVRs are built-in in the camera DSP (CXD3172AR). External EVRs shown in Table 2.1-3 are possible to use as peripheral IC. Table 2.1-3 Peripheral IC (External EVR) Peripheral IC...

  • Page 11: Clock Configuration

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 2.2. Clock Configuration 2.2.1. 1 clock / digital encoder system configuration DSP can be operated by using only one clock in this system. The clock for driving system in DSP is generated by supplying the clock for encoder (ECK).

  • Page 12: Output Configuration

    Fig 2.3-1 Signal Path of Analog Composite (YCMIX) Output System 2.3.2. Digital Output System Configuration (REC656, REC601) SS-HQ1 has two digital output modes. One is the output which is compliant with ITU REC656. The other is the output which is compliant with ITU REC601.

  • Page 13: Peripheral Circuits

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3. Peripheral Circuits 3.1. Initially Occupied Terminals 3.1.1. If No Valid Data in EEPROM If there is no valid data in EEPROM (AK6480AF or BR9080AF-W), data is read from internal memory of CXD3172AR.

  • Page 14: Processing Of Empty Pins

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.2. Processing of Empty Pins 3.2.1. Processing of Empty Pins in Each Mode Perform pin processing for the CXD3172AR depending on each mode as follows. Table 3.2-1 Processing of Empty Pins in Each Mode...

  • Page 15: Processing Of Empty Pins In Case Dac Is Not Used

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.2.2. Processing of Empty Pins in case DAC is not used When Y-DAC and C-DAC are not used by YCMIX output (DACMODE=0[h]), digital output, etc. Perform pin processing for the CXD3172AR as follows.

  • Page 16: Oscillator Circuit Periphery

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.3. Oscillator Circuit Periphery 3.3.1. Clock oscillator circuit for 1 clock/digital encoder system Providing an encoder clock (ECK) for the CXD3172AR enables internal generation in the CXD3172AR of the clock that drives the system.

  • Page 17: Clock Oscillator Circuit For 2 Clock/Eck Master Mck Pll

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.3.2. Clock oscillator circuit for 2 clock/ECK master MCK PLL Operate the CXD3172AR with two clocks: the encoder clock (ECK), oscillated by X'tal, and the driving system clock (MCK), oscillated by PLL.
  • Page 18 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Fig 3.3-3 shows the configuration and evaluation board circuit constants (Table 3.3-3) for a clock oscillator circuit for MCK PLL using LC. 1000p ESCI ESCO CXD3172AR PCOMP 1000p TC7SA04F 100k 1000p...
  • Page 19 These three figures give examples of oscillator circuits introduced with the SS-HQ1 evaluation board: Fig 3.3-1, Fig 3.3-2, and Fig 3.3-3. The circuit constants presented here has been verified in operation using a Sony evaluation board equipped with the crystal oscillator shown in Table 3.3-4. Understand that no performance guarantee is implied for different board layouts, component selection, or temperature characteristics.

  • Page 20: Reset Circuit

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.4. Reset Circuit 3.4.1. Outline This circuit performs system reset to enable stable operation when the CXD3172AR and peripheral ICs start up after power is supplied. However, problems may also be caused by a transient power supply. For a reliable way to avoid such problems, add a circuit that meets the following conditions.

  • Page 21: Ics Requiring Reset After Power-On

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Vout 500nsec 500nsec or more or more TIME [sec] Fig 3.4-2 Timing Chart 3.4.3. ICs Requiring Reset after Power-On Of the ICs used by the SS-HQ1 system, only CXD3172AR must be reset.

  • Page 22: Evr Connection

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.5. EVR Connection 3.5.1. Integrated EVR and Reserved Channels (AGC control) The CXD3172AR is equipped with a 3-channel, 8-bit D/A converter (EVR). It can produce nearly linear voltage up to approximately 0V-3.3V.
  • Page 23 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 EVR0 can be controlled by means of the user settings shown in Table 3.5-2 Integrated EVR User Settings without relying on firmware control. These are also the user settings for EVR1.

  • Page 24: Communication Control With An External Evr

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.5.2. Communication Control with an External EVR External EVR Connection As for external EVRs, the CXD3172AR can be connected to the Fujitsu MB88347L. External EVRs enable control of eight channels through the following parameters. Note that each parameter controls specific pins, so be sure to refer to the following settings if an external EVR is used.
  • Page 25 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 External EVR Chip Selection Pin Connection Chip selection signal output from the CXD3172AR of the external EVR offers control through connection to one of the following pins depending on the CSEVRSEL parameter setting. Initial setting is CSEVRSEL=0[h] and a chip selection signal is outputted from pin S4.

  • Page 26: Noise Countermeasures

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.6. Noise Countermeasures 3.6.1. Introduction Important Information for Mounting We recommend a board design of four layers or more to reduce as much noise as possible at the stage of board design.

  • Page 27: Countermeasures For Areas Around Individual Devices

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.6.2. Countermeasures for Areas around Individual Devices Countermeasures for the CCD and Surrounding Areas 1. To prevent noise from entering the CCD, be sure the ground pattern is sufficient and connect individual LC filters to power supply pins VDD (+15V or +12V) and VL (-5.0V or -7.0V) to keep the power supply...
  • Page 28 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Countermeasures for the CXD3172AR and Surrounding Areas 1. For the power supply of AVD 1-6 (pins 2, 21, 29, 55, 56, and 74) and SVD 1 and 2 (pins 50 and 100), connect LC filters by the source to prevent crosstalk from other circuits causing interference.
  • Page 29 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 7. For a two-clock system configuration, design the layout to ensure separation of the oscillator circuits that generate the clocks for input to the encoder clock input pin ECK (pin 88) and system drive clock input pin MCK (pin 43).

  • Page 30: If Noise Occurs

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.6.3. If Noise Occurs If noise on the screen from in the designed board is confirmed, identify the source of the noise before taking appropriate measures. Means of identifying noise sources are described below.

  • Page 31: External Lpf

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.7. External LPF 3.7.1. Outline The CXD3172AR contains an LPF with improved characteristics, so sufficient performance can be obtained even if an LPF is not connected to the luminance signal output pin IOY (pin 75).

  • Page 32: Example Bpf Characteristics

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.8.3. Example BPF Characteristics The following graph shows example characteristics measured on an evaluation board using the BPF formed in Fig 3.8-1. 3.58MHz NTSC BPF FREQUENCY [MHz] Fig 3.8-2 Example BPF Frequency Characteristics (NTSC) 4.43MHz...

  • Page 33: Dac Mode And Yc-Mix External Analog Circuit

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.9. DAC Mode and YC-mix External Analog Circuit 3.9.1. DAC Mode Either composite signal output or component signal output can be selected as the analog signal output method for output from the CXD3172AR. Refer to Table 3.9-1 below to set the appropriate setting for the output method you want to use.

  • Page 34: Circuit Configuration For Component Output

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.9.2. Circuit Configuration for Component Output When component output is used (DACMODE=1[h]), the CXD3172AR’s internal DAC (2ch) outputs Y/C signals through the IOY pin (pin 75) and IOC pin (pin 67), respectively. Fig 3.9-1 illustrates an example circuit for component output.

  • Page 35: Circuit Configuration For Composite Output

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3.9.3. Circuit Configuration for Composite Output When composite output is used (DACMODE=0[h]), the Y/Composite signals are mixed inside the CXD3172AR and output through the IOY pin (pin 75). With this configuration, the IOC pin (pin 67) is not used. Fig 3.9-2 illustrates an example circuit for composite output.

  • Page 36: Optical Filters

    * SV-T618S (* made by KYOCERA KINSEKI Corporation) Sony uses the optical LPFs (three-layer configuration) shown in Table 3.10-1 for all function and performance evaluations, including high resolution. Note that Sony does not support two-layer configurations or optical LPFs lacking an IR cut filter.

  • Page 37: Parameter Configuration

    4.1. Communication Parameter Concept 4.1.1. Communication Category Concept The communication parameters for SS-HQ1 are divided into the 24 categories shown below. Communication categories are divided into separate segments for each control target, so that the byte positions of the individual parameters are easy to remember.

  • Page 38: Parameter Control By Built-In Cpu

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 4.2. Parameter Control by Built-in CPU 4.2.1. Processing by CPU Processing by CPU consists of initial (power-on/sequence) processing and main processing. Note that the settings below are valid for only one initial process.

  • Page 39: Parameter Changes Through Communication

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Various applications are available for main processing by the CPU. All applications run by default. < Main Applications > Adjustment mode : Adjustment of AGC min, Pre-WB, and so on. Ext-Sync...

  • Page 40: Saving Parameters To Eeprom

    EEPROM, the firmware controls need to be stopped beforehand and the register values changed (temporarily stored) beforehand. The address map to EEPROM shown in the figure below is accessed in SS-HQ1. Mapping is performed in 1-byte units, therefore, the address length becomes 512 words x 2 bytes = 1024 bytes, address (0-3FF[h]).

  • Page 41: Eeprom All Write" Command

    (3) Send all parameters while retaining CPUHOLD=1[h], and store it temporarily in the register in DSP. To send all parameters with the SS-HQ1 control software, click the All Write button in the Register Read/Write menu. For communication with external microcomputer, send all bytes of each category to the DSP.

  • Page 42: Power-On Sequence

    5. Power-on Sequence 5.1. Power-on Sequence In the SS-HQ1 system, only initial operations for the DSP (CXD3172AR) are required after startup. Initial operations for the DSP assume that power has been supplied to the CCD and peripheral ICs. Connect reset input XRST (pin 11) to the reset circuit.
  • Page 43 RS-232C. communication Fig 5.1-2 Detailed DSP (CXD3172AR) System Initialization Sequence for SS-HQ1 Important ▪ After reset is canceled (XRST L-> H), EEPROM is still accessed for 80 ms, so save XRST=H. During this time, if the power is cut or the system is reset again, the data stored in EEPROM may be corrupted.

  • Page 44: Parameters Exclusively For Initialization

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 5.1.2. Parameters Exclusively for Initialization Parameters in the following table are only valid during initialization operations. After the initialization, both external communication and port driver control are disabled. To change this, the following procedure is required: (CPUHOLD) ->...

  • Page 45: Ccd Type Selection

    Note that the types shown below are the types supported at the time these Application Notes were prepared. Some types may be added or eliminated due to CCD version upgrades or discontinued production. Table 6.1-1 CCD Image Sensors Supported by the SS-HQ1 Number of pixels...

  • Page 46: List Of Clock Configurations For Each Ccd Type

    Ver.1.0.0 January 7, 2005 6.2. List of Clock Configurations for Each CCD type The basic clock system for the SS-HQ1 comprises both an oscillator and a PLL that uses two types of oscillators. In addition, the clock system of 4MCK (or 2MCK), 8fsc and 27MHz can be constituted for every type of CCD as operation mode.

  • Page 47: Important Information On Wiring

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 6.3. Important information on Wiring The drive circuit must be changed according to the type of CCD used. The main differences are as follows. 1. Changes in the drive circuit due to different CCD image sensor drive specifications 2.
  • Page 48 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 +15V ICX404/405AK ICX408/409AK AVS2 CXD3172AR AVD2 +15V -7.0V Fig 6.3-1 SS-HQ1 CCD Drive Circuit Example (ICX404/405AK, ICX408/409AK) ICX206/207AK ICX278/279AK AVS2 +3.3V CXD3172AR AVD2 +15V -7.0V Fig 6.3-2 SS-HQ1 CCD Drive Circuit Example (ICX206/207AK, ICX278/279AK)
  • Page 49 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 ICX226/227AK ICX228/229AK AVS2 +3.3V CXD3172AR AVD2 +12V -5.0V Fig 6.3-3 SS-HQ1 CCD Drive Circuit Example (ICX226/227AK, ICX228/229AK) ICX254/255AK ICX258/259AK AVS2 CXD3172AR AVD2 +15V -7.0V Fig 6.3-4 SS-HQ1 CCD Drive Circuit Example (ICX254/255AK, ICX258/259AK)

  • Page 50: Clock System Changes

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Fig 6.3-1 SS-HQ1 CCD Drive Circuit Example (ICX404/405AK, ICX408/409AK) shows the drive circuit when using 1/3 type CCD image sensors (ICX404/405AK, ICX408/409AK). Both Vsub voltage and RG voltage are adjustment-free. Vsub is a voltage generated inside the CCD and is used to clamp the shutter pulse, so an external clamping circuit is not required.

  • Page 51: Clock System Selection

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 6.3.4. Clock System Selection The internal clock of CXD3172AR is switched according to the operation mode. Please wire the VDD or GND side from P12 to P15 setup of CXD3172AR and set by pull up/down according to the system conditions to be used.

  • Page 52: Wiring Changes When Eeprom Is Not Written

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 6.3-3 Operation Mode in MODESEL and System Condition System condition MODESEL Operation mode 0[h] Analog / Digital output 1[h] 8fsc Analog output MCK input configuration 2[h] 27M master MCK PLL...

  • Page 53: Ccd Primary Color Separation Matrix

    4. Operate Initialization processing 6.4.2. Recommended Parameter’s Value The spectral characteristics of the color filter differ according to the type of CCD. The SS-HQ1 initial settings are designed in consideration of the spectral characteristics of a 1/4 type CCD image sensor. Therefore, resetting the parameters on the following table and writing this data to the EEPROM is recommended when using other types of CCD image sensors.
  • Page 54 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 6.4-2 CCD Types and Linear Matrix Parameters (Reference Values) 2 (PICT1) Byte 0 to 7 0 to 7 0 to 7 0 to 7 Parameter name RYGAIN1 BYGAIN1 RYHUE1 BYHUE1...

  • Page 55: Power Supply

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 7. Power Supply 7.1. Supply Voltage The SS-HQ1 requires the following four types of power supplies as the system power supplies. : Analog power supply for CXD3172AR +3.3V Logic power supply for CXD3172AR...

  • Page 56: Power Consumption

    7.1.2. Power Consumption Examples of measured current consumption values when driving ICX408AK are shown in the table below. These values were measured using a Sony Semiconductor evaluation board, and should be used as reference values. Table 7.1-2 Power Consumption Measurements(when driving ICX408AK)

  • Page 57: Level Diagram

    The SS-HQ1 system sets up the dynamic-range of 2.5 times the standard level. A level diagram for an SS-HQ1 system is described below. The recommended values and signal levels presented here have been verified on our evaluation boards. Please note that this is no guarantee of performance, including board layout changes, parts selection, and temperature characteristics.
  • Page 58 600 - 1000 [mV]. To ensure the dynamic-range of 2.5 times the standard level, the standard CCD output (Y-level) of the SS-HQ1 is 250 - 400 [mV]. The exposure time and the output level of CCD can be controlled by the shutter pulse of built-in TG of CXD3172AR.
  • Page 59 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 8.1.1.3. The Input of A/D Converter VRT(2.35[V]) 1023 VRB(1.35[V]) Fig 8.1-4 an example of 10 bit-A/D conversion DRVOUT level = A/D converter input level : Standerd signal level = 400[mV] -> D range of 2.5 times.
  • Page 60 The Fig 8.1-5 shows luminance signal processing with the NTSC form and relations with the standard output level of Y-DAC. SS-HQ1 system sets up the standard output level of the luminance signal (with gamma processing) as NTSC-100[IRE] when an A/D input level is the standard 400[mV]. And Sync-level as NTSC=-40[IRE] is added, too.

  • Page 61: The Standard Level Diagram Of Digital Outputs

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 8.1.2. The Standard Level Diagram of Digital Outputs 160 [%] Upper Limit 254 [d] 109 [%] 235 [d] 100 [%] Lower Limit 16 [d] 400 [mV] 1000 [mV] AD INPUT Fig 8.1-6 Digital output (Y signal) characteristics Digital output at 8 bits is defined in ITU-R-BT.656 and 601 as follows:...
  • Page 62 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 CXD3172AR P15_msb P08_lsb RECYGAIN RECRYGAIN RECBYGAIN Fig 8.1-7 Digital output configuration The data immediately preceding Y-DAC and ENC in analog output are used, so Y and C signal processes are the same as for analog output.

  • Page 63: Rs-232C Communication And Communication With Peripheral Ics

    9.1. RS-232C Communication 9.1.1. Interface The SS-HQ1 system supports the RS-232C format (half duplex mode) as a means of communication with external PCs. However, RS-232C communication requires an external IC for converting the 3.3V logic to the RS-232C level (recommended product: MAX3232, made by Maxim), as well as pin settings. Please see the application circuit we have provided for information on the connections with the MAX3232 and the RS-232C connector (D-sub 9 pin).

  • Page 64: Communication Procedure

    EEPROM write/read processes, have been optimized for the SS-HQ1 system, so you do not have to worry about factors like communication format and byte length. The following settings should be used in the PCs.

  • Page 65: Communication Timing

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 9.1.3. Communication Timing The CXD3172AR acquires data in byte increments according to a timing determined by the communication speed from the point in time that SI falls. Serial output is output after all data have been acquired.

  • Page 66: Communication Format

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 9.1.4. Communication Format A single packet consists of 2 to 32 bytes. After receiving one packet of data, the CXD3172AR analyzes the data and performs command execution controls. See Table 9.1-4 for the command specifications.
  • Page 67 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 < Explanation of command specifications > ▪ Data in byte 1 : Total valid byte count in one packet ▪ Data in byte 2 (CMD) : Command code Setting range : 01[h] to 07[h] ▪...

  • Page 68: Serial Communication Prohibited Period

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 9.1.5. Serial Communication Prohibited Period A serial communication prohibited period is set during the time period preceding and following the VD fall. Communication from the exterior is not accepted during the periods shown in the diagram below.

  • Page 69: Communication With Peripheral Ics

    9.2.1. Connection of Communication Bus between DSP (CXD3172AR) and Peripheral ICs With the SS-HQ1 system, the DSP (CXD3172AR), EEPROM (AK6480A or BR9080A) and EVR (MB88347L) are connected through serial communication and the peripheral ICs are controlled through the DSP in order to realize various functions.

  • Page 70: Serial Communication Speed And Timing

    CXD3172AR’s firmware, you do not need to worry about the format or speed. (Please use the EEPROM and EVR products recommended by Sony.) Note that these settings cannot be customized by the user.
  • Page 71 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 External EVR communication timing Communication with an external EVR is performed every field. The settings in the user-setting parameters EVRUSER0 to EVRUSER7 (CAT18_Byte8 to 15) are sent and applied to the MB88347L’s output voltages AO1 to AO8. For details, see “3.5.2 Communication Control with an External EVR”.
  • Page 72 EEPROM communication timing The CXD3172AR communicates with an EEPROM, which is used to store parameter settings. The EEPROMs recommended by Sony are AK6480AF (Asahi Kasei) and BR9080AF (Rohm). The firmware in the DSP automatically identifies the EEPROM. Parameters are assigned in byte increments to EEPROM addresses. Addresses in byte increments are specified both when reading EEPROM address specifications and writing EEPROM address specifications.

  • Page 73: Clock For Communication With Peripheral Ics

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 9.2.4. Clock for Communication with Peripheral ICs All data are CXD3172AR design values. Communication is LSB-first. The CASCK frequency varies depending on the frequency of the X’tal connected to the ECK (pin 88). Note that this frequency is uniquely determined by the DSP firmware and cannot be set by the user.
  • Page 74 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 EEPROM CSROM CASCK CASO <COMMAND> <ADDRESS> <DATA> 5th to 8th bit 9th to 32th bit 1st to 4th bit Fig 9.2-4 Communication Protocol – EEPROM Write - CSROM CASCK CASO CASI <ADDRESS>...
  • Page 75 Ver.1.0.0 January 7, 2005 The SS-HQ1 system does not have a pin for inputting the EEPROM BUSY state. Therefore, the BUSY state is monitored using a timer, with a WAIT process (10ms or longer) performed each time one word is written.
  • Page 76 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Limitations when Using EEPROM When using an empty EEPROM for the first time, first perform a full EEPROM write. If the system starts without an EEPROM, do not perform an EEPROM category specification write (a full write can be performed).

  • Page 77: Description Of Operation Of Each Function

    10.1. Port Driver Function 10.1.1. Port Driver Function Description The SS-HQ1 system has port driver functions. With port driver functions, internal parameters can be used for operations by means of switches connected to P0 to P15 (Pins 91 to 94, 96 to 99, 76 to 80, and 82 to 84) of CXD3172AR.

  • Page 78: Port Driver Setting Method

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.1.2. Port Driver Setting Method This section explains the setting method for the port driver functions. Description of Port Driver Parameters Port drivers are configured by means of parameter CAT20 Port.
  • Page 79 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.1-3 Parameters for Specifying Bits PDR “ｎ” bit Parameter Input port setting Output port setting PnADJ Coefficient parameter 4 bits (Unused) PnWID 0 to 15: bit width (1 to 16 bits) (Unused) ▪...
  • Page 80 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 When PnADJ sets it as 0[h]-7[h] The coefficient can be selected from 0 to 0.875 times. The parameter value = The value written to EEPROM x PnADJ / 8 (This parameter value is set by high input of port driver.) When an input port is “High”, the setting value is calculated by multiplying the parameter value written to...
  • Page 81 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 * When the setting value changes to values other than 0[h] and 0[h], the port input should not be set to 0[h] by Low (value written to EEPROM). Coefficient operation is performed to the value written to EEPROM. Thus, the change of the value by the Low/High input to a port driver cannot be performed.

  • Page 82: Parameter Setting Instructions

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.1.3. Parameter Setting Instructions To control a 1-bit parameter with the port driver (Example 1) Assign PGON (CAT9_Byte36_bit3) to P2 of the port driver, and from High or Low input to P2 (Pin 93), generate a pattern generator.
  • Page 83 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 To control a multi-bit parameter with the port driver (Example 2) Assign the 8-bit wide parameters of PGPAT (CAT2_Byte37_bit0-7) to P1 of the port driver. From High or Low input to P1 (Pin 92), change the GAIN value of RYGAIN1.
  • Page 84 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 To watch the state of a parameter with the output port driver (Example 3) Assign MIRROR (CAT1_Byte1_bit4) to P3 of the port driver, and set the output of P3 (94PIN) to change High or Low by parameter value of MIRROR.

  • Page 85: Field Processing For Each Port Driver

    10.1.4. Field Processing for Each Port Driver To reduce the processing load, the SS-HQ1 system divides the port driver processing. Of the 16 ports, four are controlled by individual 1V (fields), and processing for the other 12 is by every 3V (fields).

  • Page 86: Precautions For Port Driver Configuration

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.1.6. Precautions for Port Driver Configuration • Parameters assigned to port drivers cannot be externally controlled. When external control is desired, control must be terminated by removing the port driver assignment or by completing the following parameter settings.

  • Page 87: Port Driver Setting Example

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.1.7. Port Driver Setting Example The basic setting method for port drivers is as follows. If reset after writing to EEPROM (Example) Set up the switching control of the 8-bit parameter AESPEED. (CAT14_Byte12_bit0-7).

  • Page 88: Conditions For Disabling The Port Drivers

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.1.8. Conditions for Disabling the Port Drivers Port driver control is disabled under the following conditions. Suppression by the parameters Port drivers do not function with port driver parameters CPUHOLD = 1[h] or PDRHOLD = 1[h].

  • Page 89: Y Signal Processing

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.2. Y Signal Processing 10.2.1. Y (Luminance Signal) Processing Flow The Y (luminance signal) signal is processed through the block shown below. Y main PRE / Blemish Compensation OB INT Process...
  • Page 90 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Black level digital clamping PBLK PBLK CLPOB CLPOB DRVOUT DRVOUT Signal Level OFFSET with OFFSET AGC Noise = Black Level AD Input Level VRB = Blankng VRB = Blankng AGCCONT =MIN AGCCONT =MAX Fig 10.2-2 DRVOUT (AD input signal) and offset level...
  • Page 91 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.2-2 Digital clamp parameter Parameter Address Description CAT22_Byte6_bit0-3 (MSB) S1 series OB area integrated value (output-only parameter). OBLKS1 CAT22_Byte4_bit0-7 (LSB) BLACKS1 is calculated by the internal firmware. CAT22_Byte6_bit4-7 (MSB) S2 series OB area integrated value (output-only parameter).

  • Page 92: Y Signal Main Process

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.2.3. Y Signal Main Process Y Main Process Block Wclip Mask Gamma Gain Delay Aperture Compensation High Resolution Fig 10.2-5 Y Signal Main Process block The Y signal main process includes the following: •...
  • Page 93 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Detail Enhancement When DEON (CAT2_ Byte10_bit7) is set to 1[h], the SS-HQ1 system’s built-in detail enhancer operates, enhancing faint signals that are hidden by ordinary aperture compensation. The available enhancement level settings are as follows: DELVSEL (CAT2_ Byte11_bit0) = 0 [h]: Weak;...
  • Page 94 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 High Luminance Clip (White Clip) The high luminance level can be clipped in the final output of the Y signal. This function can be used as a maximum output limiter. WCLIP=7[h]...

  • Page 95: High Resolution Mode

    10.2.4. High resolution mode The high resolution mode of SS-HQ1 is able to realize by using a general lens and general optical LPF. We use the optical LPF of Kyocera Kinseki, Ltd. in our evaluation board. Please refer to the chapter “3.10 Optical Filters”...
  • Page 96 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 High resolution signal processing algorithm A high resolution signal processing line is added in parallel to the main line of luminosity signal processing. The flow of signal processing is as follows.

  • Page 97: Aperture Compensation Function

    Ver.1.0.0 January 7, 2005 10.2.5. Aperture Compensation Function Aperture Compensation processing performed by the SS-HQ1 includes H aperture compensation processing, V aperture compensation processing, VH aperture compensation processing which adds V and H aperture compensation processing, and highlight aperture compensation processing which boosts the aperture compensation of highlighted portions after gamma.
  • Page 98 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.2-8 VH Aperture Compensation Related Parameters Parameter name Description Initial value Sets the gain after adding V and H aperture CAT2 VHAPG compensation. Byte4_bit2-5 from x0(0[h]) to x2(F[h]) CAT2 Applies slice after adding V and H aperture...

  • Page 99: Chroma Signal Processing

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.3. Chroma Signal Processing 10.3.1. Block diagram Chroma Processing Block Linear Blemish Comp Matrix Gamma Matrix DL13 H/W parameter registers CAT2_PICT1,CAT4_AWB1 INTG INTG F/W control parameters CAT12_CPU, CAT13_PICT2, CAT15_AWB2 Fig 10.3-1 Chroma Signal Processing Block Extracts RGB primary color signal from the output signal of complementary color filter CCD, performs white balance and gamma processing, and generates R-Y signal and B-Y signal for video output.

  • Page 100: Complementary Color Pixel Clipping

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 WB(White Balance Gain Circuit) The change in white color under conditions of the photographed subject such as color temperature, are corrected by changing the gain ratio of R, G, B in F/W control (AWB). Refer to "10.7 WB operation".

  • Page 101: Highlight Edge Color Compensation Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.3.3. Highlight Edge Color Compensation Function When a subject with very large contrast differences is shot, the edges of the subject may be colored. This function temporarily changes the chroma LPF characteristics, making it possible to reduce the apparent amount of edge coloring.

  • Page 102: Using Four-Quadrant Independent Control

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.3.4. Using Four-Quadrant Independent Control The CXD3172AR can set HUE/GAIN for R-Y and B-Y data independently in four quadrants on the R-G/B-G axes prior to conversion to R-Y/B-Y. The setting procedure is described below.
  • Page 103 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 4. Adjust HUE/GAIN for each quadrant through parameters. Adjust HUE/GAIN for each quadrant through the parameters listed below. The HUE/GAIN adjustment parameters for the first quadrant (RYGAIN1, BYGAIN1, RYHUE1, BYHUE1) also serve as the HUE/GAIN adjustment parameters for four-quadrant simultaneous control.

  • Page 104: False Color Suppress Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.3.5. False Color Suppress Function The chroma block has a function for suppressing the chroma signal using the hardware according to the luminance level or V aperture correction level after conversion to R-Y/B-Y.

  • Page 105: Variable Gamma Function

    GAMSEL= 1 Fig 10.4-1 Gamma Curve Selection The SS-HQ1 system’s DSP (CXD3172AR) has an internal gamma correction circuit. The parameter GAMSEL (CAT12_Byte7_bit0) can be used to switch between User Gamma 0, which is saved to EEPROM for use, and User Gamma 1, which can be changed at immediately through serial communication. Use either of these two values according to the particular application.
  • Page 106 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 To change the gamma curve, select the setting parameter in Table 10.4-2 “Gamma curve parameters (luminance signal)” and set the gamma area (nonlinear) and knee (KNEE) area (linear). Details on each parameter are discussed later.

  • Page 107: Y Variable Gamma

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.4.2. Y Variable Gamma Any of the curves shown in Fig 10.4-2 “Y variable gamma” can be selected through combinations of YGAMSEL and YKNEESEL (when GAMSEL=0[h]), or UYGAMSEL and UYKNEESEL (when GAMSEL=1[h]).

  • Page 108: Y Gamma Off

    The Y variable gamma curve characteristics can be checked using the PG function built into the DSP (CXD3172AR) of the SS-HQ1 system. Output a Raster Horizontal Ramp (see Fig 12.5-2), referring to 12.5 “Pattern Generator (PG)”. The curve characteristics can be checked as changes in the horizontal direction luminance signal level through monitoring using an oscilloscope or waveform monitor.

  • Page 109: Y Gamma Curve Compression In Low Luminance Areas (S Gamma)

    The closer the AD input is to 0 (black level), the stronger the elongation will be. As a result, changes in luminance near the black level seem to be very large. The DSP (CXD3172AR) in the SS-HQ1 system also has a function for compressing the low areas of the gamma curve.

  • Page 110: Chroma Variable Gamma

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.4.5. Chroma Variable Gamma The following table summarizes the chroma signal gamma curve parameters. Table 10.4-3 Gamma Curve Parameters (Chroma Signal) Parameter Setting Type Address Description Name Value Chroma signal CAT2_Byte30_bit0-2...
  • Page 111 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 CKNEE=5 100 [%] 78 [%] CKNEE=0 CGAMMA=7 CGAMMA=0 100 [%] 200 [%] INPUT Level Fig 10.4-5 Chroma Variable Gamma Note: The curves shown in “Fig 10.4-5 Chroma variable gamma”, are model curves. They do not represent actual measurements.

  • Page 112: Chroma Gamma Off

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.4.6. Chroma Gamma OFF Like Y gamma OFF, chroma gamma OFF can be used to select a line shown in “Fig 10.4-6 Chroma gamma OFF”, if you want to make the chroma output level linear.

  • Page 113: Chroma Signal Knee Clipping Process

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.4.8. Chroma Signal Knee Clipping Process In cases where the chroma variable gamma circuit input level exceeds 200%, the knee output can be clipped to a constant level. CKNCLIP=1 160 [%]...

  • Page 114: Opd Window Setting And Display

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.5. OPD Window Setting and Display 10.5.1. Detection Window Setting Method The CXD3172AR's OPD (detection integrating circuit) has an AE/AWB common detection window generation circuit. It also has a function for displaying the detection window on the screen.
  • Page 115 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.5-1 Detection Window Setting Parameters Parameter name Description Setting unit UOPDWHST (Normal) 4 pixels (CAT16_Byte1_bit0-7) Detection window horizontal start position UOPDWHSTM (Mirror) 4 pixels (CAT16_Byte2_bit0-7) Detection window horizontal start position...

  • Page 116: Detection Window Screen Display

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.5.2. Detection Window Screen Display We recommend displaying markers on the screen when adjusting the detection window. Table 10.5-3 Detection Window Display Parameters Parameter name Description Note UOPDWMK Displays detection window on (CAT16_Byte8_bit0) monitor when set to “1[h]”...

  • Page 117: Ae Operation

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.6. AE operation 10.6.1. Sequence of Operation START Processing is branched in modes accepting from Mode selection DIP switches or serial communication input. ME mode? Calculation of In ME mode, fixed shutter speed and fixed gain...

  • Page 118: Mode

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.6.2. Mode Switching among BLCOFF, AEREF, FLC[0], AGCMAX, AEME, and AESHUT enables selection of the operating mode as well as activation and deactivation of additional functions. As for the switching method, in some cases switching is done by means of DIP switches and in others, by serial communication.
  • Page 119 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 AE Mode AE mode can be activated by setting AEME (CAT CAT14_Byte1_bit0) to 0[h]. This mode offers AE operation through AGC and electronic iris control. AE here essentially controls exposure by means of the electronic iris with AGC at the minimum required gain.
  • Page 120 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 AESHUT Mode AESHUT mode can be activated in AE mode by setting AESHUT (CAT14_Byte1_bit6) to 1[h]. At this time, the shutter speed can be set with SHUTMAX, SHUTMIN, SHTSEL, and LLFLC. (See the table "Setting the Shutter Speed.") The electronic shutter speed is selected in SHTSEL.
  • Page 121 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.6-5 Example of Setting the Shutter Speed (PAL) LLFLC SHUTMAX SHUTMIN SHTSEL Shutter Speed [sec] 1/50 1/120 1/250 1/500 1/1,000 1/2,000 1/4,000 1/10,000 1/100,000...

  • Page 122: Backlight Compensation

    Ver.1.0.0 January 7, 2005 10.6.3. Backlight Compensation The SS-HQ1 system offers a backlight compensation function. This backlight compensation mode can be switched ON and OFF in BLCOFF (CAT14_Byte1_Bit2). As for the compensation method, it can be set to weighted average mode or compensation gain fixed mode by switching BLCSEL (CAT13_Byte4_Bit0).

  • Page 123: Flickerless Function

    1024.0 10.6.4. Flickerless Function A flickerless function is available with the SS-HQ1 system. Flickerless mode is explained in the "Table 10.6-8 Flickerless Mode." Modes are selected through the parameters for NORMFLC, LLFLC, and FIXSHTFLC as indicated in the table.

  • Page 124: Ae Hysteresis Function

    Ver.1.0.0 January 7, 2005 10.6.5. AE Hysteresis Function AE hysteresis function is available with the SS-HQ1 system. Using this function can enhance AE stability, even in moments when the luminance level changes, such as when objects momentarily cross in front of the screen.
  • Page 125 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.6-11 AEWAIT AEWAIT AE WAIT time Category CAT14_Byte11_bit0-7 (8bit) Outline The hysteresis counter can be set. Conditions AEHYST>0, AEWAIT>0, AEHYST>AESTAB Available settings range 00[h] to FF[h] 8bit Initial value 0[h]...

  • Page 126: Ae Mechanical Iris Mode

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.6.6. AE Mechanical Iris Mode This is an example of a lens with an automatic iris which operates using a power supply and video signal. In AE mode, if MIRIS (CAT14_Byte1_bit1) is set to 1[h], then Mechanical Iris Mode is set.
  • Page 127 Fig 10.6-4 is an example in which a Rohm BA7655AF is used as the VCA, and a control range of -12dB to 0dB is used when there is backlight. The maximum value is 0dB, with VCA0=VCAP6=VCAP12. Sony has only evaluated controls (with backlight) in the range of VCA -12dB to 0dB.

  • Page 128: Me Shutter Speed And Agc Gain Setting

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.6.7. ME Shutter Speed and AGC Gain Setting ME mode can be activated by setting AEME (CAT CAT14_Byte1_bit0) to 1[h]. In ME mode (short for "manual exposure" mode), the shutter speed can be set with SHUTMAX, SHUTMIN, SHTSEL, and LLFLC. (See the table "Setting the Shutter Speed.") The method for selecting the electronic shutter speed is the same as for...

  • Page 129: Detailed Description (Relationship Of Modes And Parameters)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.6.8. Detailed Description (Relationship of Modes and Parameters) Table 10.6-14 AGCMAXL AGCMAXL ae AGC MAXimum gain Low Category CAT14_Byte15_bit0-7 (8bit) Outline Enables the AGC maximum gain to be set. Conditions AGCMAX=0[h] setting...
  • Page 130 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.6-16 AGCMIN AGCMIN ae AGC MINimum gain Category CAT19_Byte1_bit0-7 (8bit) Outline Enables the AGC minimum gain to be set. Conditions Available settings range 00[h] to FF[h] 8bit Initial value 28[h]...
  • Page 131 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.6-17 AEUSR AEUSR AE USR setting level Category CAT14_Byte13_bit0-7 (8bit) Outline The AE convergence exposure (AE reference) can be set. Conditions AEREF=1[h] (USR) Available settings range 00[h] to FF[h] 8bit...

  • Page 132: Wb Operation

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.7. WB operation 10.7.1. Sequence of Operation (1) Processing branches according to the START mode input by the DIP switches or serial input. Mode selection (2) In fixed value mode, the fixed gain is selected, the signal is sent to the WB gain amplifier.

  • Page 133: Wb Operation

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.7.2. WB Operation The modes shown in “WB Modes” can be selected by switching AWBMODE(CAT15_Byte1_bit0-3). Table 10.7-1 WB Modes MODE AWB1 AWB2 AWB3 AWBMODE Manual White Balance Push Hold User fixed value 1...
  • Page 134 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 MWB (Manual white balance) When adjusting the R gain, the B gain is also adjusted following the black body radiation curve. SFTUP and SFTDWN in Table 10.7-3 are respectively set to port drivers to perform adjustments through key operations.
  • Page 135 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.7-4 Parameters controlled through keys Parameter Description WBR(CAT4_Byte1) White balance gain R WBB(CAT4_Byte3) White balance gain B Table 10.7-5 Parameter for saving WBR/WBB adjustment value Parameter Description Push lock R gain...
  • Page 136 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 User fixed value In this mode, the white balance gain is set to a preset value. Four different patterns of setting values can be stored. The default values are as shown in the "Table 10.7-7 User fixed value".

  • Page 137: Atw Operation Range

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.7.3. ATW Operation Range ATW sets an operation frame that follows the black body radiation curve. The operation color temperature range (R-B axis direction) for the standard operation frame is from approximately 2500 K to approximately 9500 K.

  • Page 138: Atw Related Parameters

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.7.4. ATW Related Parameters Luminance specific integration Table 10.7-10 AWBSEPOF AWBSEPOF AWB SPEcific OFf Category CAT15_Byte2_bit0 (1bit) Outline ON/OFF setting for luminance specific integration. Conditions AWBMODE=0[h] Available settings range 0[h],1[h] 1bit...
  • Page 139 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.7-12 INTSLICE INTSLICE Category CAT15_Byte29_bit0-7 (8bit) Sets the maximum value on the medium luminance side of the integral Outline range for luminance specific integration. Conditions AWBMODE=0[h], AWBSEPOF=1[h] Available settings range...
  • Page 140 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.7-14 HLCUT HLCUT Category CAT15_Byte31_bit0-7 (8bit) Sets the high luminance side selection threshold value for luminance Outline specific integration. Conditions AWBMODE=0[h], AWBSEPOF=1[h] Available settings range 0[h]-FF[h] 8bit Initial value 80[h] Description Reducing this parameter makes easier to use high luminance portions.
  • Page 141 Notes Convergence point shift The SS-HQ1 has a function for shifting the convergence point. This system has the two convergence point shift modes of auto discrimination mode and select 1 point mode. Auto discrimination mode automatically discriminates the convergence point position and controls the gain. In this mode the convergence point shift can be set in four directions.
  • Page 142 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.7-19 ATWGSFT1 / ATWRSFT1 / ATWBSFT1 / ATWMSFT1 ATWGSFT 1 / ATWRSFT1 / ATW Green ShiFT1 / ATW Red ShiFT1 ATWBSFT1 / ATWMSFT1 ATW Blue ShiFT1 / ATW Magenta ShiFT1...
  • Page 143 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Dead band adjustment Table 10.7-21 WBDBAND WBDBAND White Balance DeadBAND Category CAT15_Byte14_bit0-7 (8bit) Outline Sets the dead band width for the convergence point complete judgment. Conditions Available settings range 0[h]-FF[h] 8bit...
  • Page 144 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 AWB window The weighting can be set for each OPD window. The AWB windows can be displayed on the monitor by setting UOPDWMK (CAT16_Byte8_bit0) = 1[h]. In addition, the detection frames to be displayed on the monitor can be selected by setting AWBWON (CAT4_Byte5_bit2) = 1[h] and setting UOPDDISP (CAT16_Byte8_bit 1-4).

  • Page 145: Anti Color-Rolling Mode

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.7.5. Anti Color-rolling mode When shooting with a NTSC (59.94 Hz) camera under fluorescent lighting with a 60 [Hz] power supply, cyclic color changes with a long period appear. This is called color-rolling.
  • Page 146 Notes Color-rollingless AWB mode operation frames In addition to the ATW operation frames, the SS-HQ1 also has operation frames for color-rollingless AWB mode. Two types of operation frames can be set and turned on and off independently. Table 10.7-28 CRFRMOFF...
  • Page 147 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.7-29 CRFRM1OFF / CRFRM2OFF CRFRM1OFF / anti Color-Rolling FRaMe1 OFF / CRFEM2OFF anti Color-Rolling FRaMe2 OFF Category CAT15_Byte44_bit0 (1 bit each) Outline ON/OFF settings for color-rollingless AWB operation frames. CRLESSON=1[h]...
  • Page 148 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 ・・・ Final Operation frame (R-B)/G Frame 1 Frame 2 (R+B-2G)/G Fig 10.7-5 Operation frame of Color-rollingless...

  • Page 149: Suppress

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.8. Suppress Switches the suppress ON and OFF with the following parameters. When this parameter is ON, a setup of CSPR(CAT12_Byte6_bit4) and ASPR(CAT12_Byte6_bit3) are reflected. Table 10.8-1 SPRS Parameter Description Settings range...
  • Page 150 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table10.8-4 CSPRMIN CSPRMIN Chroma SuPpRess MINimum level Category CAT13_Byte21_ bit0-7 (8bit) Outline Chroma suppress minimum level Available setting range 00[h] to FF[h] 8bit Initial value 8A[h] Description “00[h]”:Complete suppress, ”FF[h]”:No suppress Notes Table 10.8-5 CSPR...

  • Page 151: Aperture Correction Suppress

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.8.2. Aperture Correction Suppress This suppresses the aperture correction level in accordance with the AGC gain. The settings (start AGCCNT, end AGCCNT, minimum level) are changed by using the following parameters.
  • Page 152 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 10.8-9 ASPR ASPR Apcon SuPpRess Category CAT12_Byte6_bit3 (1bit) Outline Switches the apcon suppress ON and OFF Conditions SPRS=1[h] Available setting range 0 [h],1[h] 1bit Initial value 1[h] Description Notes Enabled when SPRS=1[h]...

  • Page 153: Mirror Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.9. Mirror Function The CXD3172AR contains a mirror function. The video signal which reversed right and left as shown in the following figure can be outputted by using the mirror function.

  • Page 154: Mask Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.10. Mask Function 10.10.1. Setting Procedure The CXD3172AR is equipped with a mask function. Eight masks can be produced from the serial communication data settings. The following table presents the parameters related to the mask function settings.
  • Page 155 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 The mask setting procedure is as follows. 1. Set MSKON to 1h. 2. Set the mask display positions in MSKnHSET, MSKnHRST, MSKnVSET, and MSKnVRST. 3. Set the brightness in MSKYLV and the colors in MSKBYLV and ASKRYLV.

  • Page 156: Important

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 10.10.2. Important The following points are important to keep in mind in relation to mask function settings. 1. Eight masks can be simultaneously displayed or stacked on top of each other, but it is not possible to change the brightness signal level and colors separately for each mask.

  • Page 157: Functions For Adjustment

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 11. Functions for Adjustment 11.1. Adjustment Operation Mode 11.1.1. The kind of Modes It is possible to change in six adjustment operation modes by the setting of serial communication data in CXD3172AR.
  • Page 158 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 3. Adjust the exposure level so that the video signal is 250[mVp-p] in the CCD-OUT signal. Adjust the exposure level using an ND filter, changing the iris of lens, etc. 4. Set CCDLEV to 1[h] (CCD level adjustment end).
  • Page 159 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Static Blemish Detection Mode There are two modes, which are manual mode and auto mode, in static blemish detection mode. • Manual mode The detected data are written to EEPROM by manual operation, after blemish detection in manual mode.
  • Page 160 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Blemish Detection and Compensation Modes There are two blemish detection and compensation modes (static detection and compensation functions): normal static detection and compensation mode and one-push static detection and compensation mode. (For further details on the static detection and compensation functions, see “11.2 CCD blemish detection and...
  • Page 161 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 AWB Monitor Mode Set ADJMODE to 31[h] to enter AWB monitor mode. In AWB monitor mode, the white balance gain values occurring during the AWB operation are output in AWBOUT1-3. See “Table 11.1-6 Outputs in Monitor Mode” for the gain values which are output in each parameter.

  • Page 162: Ccd Blemish Detection And Compensation

    The SS-HQ1 automatically detects and corrects blemishes in order of blemish level (starting with the highest blemish level). It can detect and correct 32 blemishes.

  • Page 163: Blemish Detection And Compensation Parameters

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 11.2.2. Blemish detection and compensation parameters Detection Area Setting These parameters set the blemish detection area. When AREA is set to “1[h]”, the detection area is displayed. The location and size of the displayed box can be changed by setting HSRTL/M, VSRTL/M, HWIDTHL/M, and VWIDTHL/M.

  • Page 164: Static Detection And Compensation Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 11.2.3. Static detection and compensation function Description of operations Detection operation A blemish is recognized by static detection, when a target pixel is more than a fixed level to a black level, while the CCD is shielded from light.
  • Page 165 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Related Parameters Blemish compensation function ON/OFF The following parameter is used to turn the blemish compensation function ON/OFF. Table 11.2-3 Blemish compensation function ON/OFF parameter Parameter Description 0[h]: Turns blemish compensation function OFF...
  • Page 166 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Blemish detection results The blemish detection results (type, level, address) are written to these parameters. Blemish detection results for a total of 32 blemishes may be written. (If there are fewer than 32 blemishes [e.g., if there are just two blemishes], the other parameters are left at their initial values and are not overwritten.)
  • Page 167 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Blemish correction count setting The maximum number of detected blemishes is always 32. However, the number of corrections is set using the following parameter. Table 11.2-8 Parameter for setting the number of blemish corrections...
  • Page 168 Ver.1.0.0 January 7, 2005 Setting procedure The SS-HQ1 has two adjustment modes for performing static detection and compensation. 1. Normal static detection and compensation mode : In this mode, detection results are manually written to EEPROM. 2. One-push static detection and compensation mode : In this mode, detection results are automatically written to EEPROM.
  • Page 169 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 CCD blemish threshold levels The blemish detection threshold level (DETREFL/M) is determined by the following equation: • DETREFL/M (10bit) = 1023×DETACCT×BLMDETAGC×(blemish level threshold value mV during accumulation of 1 field) / 1000mV •...
  • Page 170 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Fig 11.2-4 is a graph illustrating the correlation between the CCD blemish level, accumulation time (DETACCT) and threshold level (DETREFL/M). Because exposure time is less than one field in practice, the CCD blemish level is the Real (1-field) line in the graph.

  • Page 171: Dynamic Detection And Compensation Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 11.2.4. Dynamic detection and compensation function Description of operations This function holds a blemish address for each frame. It compares this address against the blemish address from N fields earlier, and if they match, a blemish is recognized. The blemish address held for each frame is an...
  • Page 172 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Detection operation (2) The only blemish address which is held is the highest-level blemish address within a frame, when the conditions of detection operation (1) are satisfied, and the target pixel is at or above a level consisting of the threshold level set in the parameter DETREFL/M plus the pixel level of each of two pixels of the same color filter which are adjacent in the horizontal direction.
  • Page 173 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Related parameters Blemish compensation function ON/OFF The following parameter is used to turn the blemish compensation function ON/OFF. Table 11.2-11 Blemish compensation function ON/OFF parameter Parameter Description 0[h]: Turns blemish compensation function OFF...
  • Page 174 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Detection threshold level settings These parameters are used to set the blemish threshold level and the large blemish threshold level. Pixels exceeding the levels set in these parameters are recognized as being blemish.
  • Page 175 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Blemish address resetting This parameter is used to reset the values of parameters storing blemish detection results (all values are set to “00[h]”). Note that if blemish detection results are written to EEPROM (blemishes detected through static detection), the EEPROM values are not reset.
  • Page 176 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Setting for number of peripheral pixels during dynamic detection With dynamic detection, one of the detection conditions is that the pixels surrounding the target pixel be at or below the dark level reference value during the normal imaging state. The following parameter is used to change the number of peripheral pixels for the target pixel (blemish pixel).
  • Page 177 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Blemish releasing level setting This parameter is used to set the releasing level for releasing detections made through dynamic detection. Table 11.2-22 Parameter for setting releasing level Parameter Description DELREFL CAT11_Byte6_bit0-7(LSB)
  • Page 178 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Setting procedure Use the following procedure to set up dynamic detection and compensation. 1. Set the dynamic detection function to OFF. (DYNDETON=0[h]) (See Table 11.2-12) 2. Set the blemish detection area. (See Table 11.2-1) 3.

  • Page 179: False Blemish Generating Function

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 11.2.5. False blemish generating function Description of operations This function generates false blemishes. The blemish level can be set as well, so use this function to check the blemish detection and compensation operations. This function may be used with both static detection and dynamic detection.

  • Page 180: Adjustment Of Tg Phase

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 11.3. Adjustment of TG Phase You can adjust phase and drive ability of high frequency TG pulse (H1, H2, RG, XSHP, XSHD, XRS). You can acquire a suitable CCD signal by adjusting phase and drive ability, and it can be well sampled. Since these phases may change with the composition of a substrate, or methods of wiring, please adjust a phase if needed.
  • Page 181 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Setting Value 1h-7h Setting Value Setting Value 8h-Fh Fig 11.3-1 Adjustment of delay Adjustment of duty Duty can be changed by the parameter of Table 11.3-3. Moreover, as shown in Table 11.3-4, a setting value is changed, and the amount of duty can be adjusted.
  • Page 182 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 11.3-4 Amount of duty adjustment Amount of Setting Value Changing point adjustment(ns) 0[h] 1[h] 2[h] 3[h] Falling edge 4[h] 5[h] 6[h] 7[h] 8[h] 9[h] A[h] B[h] Rising edge C[h] D[h]...
  • Page 183 When drive ability is set to "7[h]", each TG output terminal becomes high impedance. Therefore the pulse is not outputted. As an example, when DRBH1 is changed, H1 waveform measured on a Sony evaluation board is shown in Fig 11.3-3.
  • Page 184 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Phase relation of each signal About the phase relation of each signal, please confirm the specifications of CCD to be used and the specifications of CXD3172AR. These phases affect quality of image. Therefore, it is careful of the phase relation shown in Fig 11.3-4 , and we recommend you to confirm by the picture finally.

  • Page 185: Supporting Functions For Applications

    12.1. Using Digital Output 12.1.1. Operation Modes with Digital Output The operation modes (MODESEL) available when digital output is used with the SS-HQ1 are limited. See Appendix “13.2 Operation Mode Control during Digital Output” for details. 12.1.2. Digital Output Format Two digital output formats are supported for output from the CXD3172AR: ITU-REC601-compliant output and ITU-REC656-compliant output.

  • Page 186: Ways To Use Digital Output

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.1.4. Ways to Use Digital Output There are two types of digital output: straight output and ITU-REC output. Each piece of output data is output at the rising edge of the clock output from the DCK pin (CXD3172AR pin 90). The DCK clock can be reversed and its delay adjusted through parameter settings (see Table 12.1-3).
  • Page 187 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 254(Upper Limit) 16(Black level) 1(Lower Limit) ITU-Rec Luminance Output RECOUT=1[h] Straight Luminance Output RECOUT=0[h] Fig 12.1-1 Differences in Luminance Setting in Each Output Type (with ramp signal input) * The black level of luminance output can be varied in the range of 0[h] to 1F[h] using BLCKLV.

  • Page 188: Parameter Settings For Each Output Type

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 254(Upper Limit) 240(100%Color Bar) 16(Black level) 16(100%Color Bar) 1(Lower Limit) ITU-Rec Chrominance Output (Offset Binary) RECOUT=1[h] 144(100%Color Bar) 114(100%Color Bar) Straight Chrominance Output (2's Complement) RECOUT=0[h] Fig 12.1-2 Differences in Chroma Signal in ach Output Type (with ramp signal input, including plus/minus sign) 12.1.5.

  • Page 189: Itu-Rec656

    When ITU-REC656-compliant output is set, a timing reference code (TRC) indicating the horizontal and vertical blanking periods is multiplexed and output with the Y/Cr/Cb data. The SS-HQ1 uses the following ITU-REC-compliant codes as codes for the TRC fourth word. Table 12.1-5 ITU-REC656 TRC(Fourth word)
  • Page 190 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Horizontal timing Fig 12.1-3 summarizes the relationships between DCK, DHD, and the output data (DOUT). During horizontal synchronization, DHD falling is detected and the counter is reset. The counter maximum value is determined from each mode’s clock frequency and the TV system’s horizontal period.
  • Page 191 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Vertical timing During vertical synchronization, as in horizontal synchronization, the counter is reset when DVD falls and incremented when HD falls (see Fig 12.1-4 and Fig 12.1-5). Set the Field 1 and Field 2 blanking periods separately for each TV system in the blanking start parameters in Table 12.1-6.
  • Page 192 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Analog ODD Field　・　Digital Field 1 DFLD (Internal signal) V counter (Internal signal) TRC_F TRC_V V-blanking 24line EAV = DA[h] EAV = F1[h] EAV = B6[h] EAV = 9D[h] TRC code SAV = C7[h]...
  • Page 193 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.1-8 Blanking Parameter Recommended Values Recommended value Parameter NTSC FLD1FSTA CAT10_Byte6_bit0-2 3[h] 3[h] FLD1VSTA CAT10_Byte6_bit3-7 12[h] 18[h] FLD2FSTA CAT10_Byte7_bit0-2 3[h] 2[h] FLD2VSTA CAT10_Byte7_bit3-7 13[h] 18[h]...

  • Page 194: Using External Synchronization

    Ver.1.0.0 January 7, 2005 12.2. Using external synchronization 12.2.1. Synchronization for the SS-HQ1 system The SS-HQ1 system supports line lock, VS lock, VBS lock, V reset H reset, and other external synchronization systems. Internal mode (INT) In this mode, external synchronization is not applied.

  • Page 195: Parameters Used To Set External Synchronization

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.2. Parameters used to set external synchronization The following two parameters are used to set external synchronization modes. • ATMODEON (CAT17_Byte17_bit5) • SGMODE (CAT17_Byte17_bit0-3) With ATMODEON, the external input signal is recognized and the external synchronization mode is switched automatically based on that signal.
  • Page 196 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.2-4 Detection disabling parameters Parameter Description HDETOFF CAT7_Byte2_bit0 EXT-HD input detection 0[h]: Enable 1[h]: Disable VDETOFF CAT7_Byte2_bit1 EXT-VD input detection 0[h]: Enable 1[h]: Disable SDETOFF CAT7_Byte2_bit2 EXT-SYNC input detection 0[h]: Enable 1[h]: Disable...
  • Page 197 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.2-7 SGMODE controlled parameter values (parameters setting synchronization signal I/O pins) controlled parameters SGMODE S0IN S1IN S2SEL S3SEL S4SEL 0[h] 1[h] 1[h] 2[h] 3[h] 0[h] 7[h] 1[h] 4[h] 0[h] 7[h]...

  • Page 198: Internal Mode (Int)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.3. Internal mode (INT) In this mode, external synchronization is not applied. There are two different system configurations: a 1-clock/digital encoder system, and an ECK master–MCK PLL system. The SGMODE set value is 0[h] (see Table 12.2-5).
  • Page 199 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 2-clock/ECK master–MCK PLL system configuration This system comprises two clocks, with the encoding clock (ECK) serving as the master, and with PLL applied to the system driving clock (MCK). The master signal is the encoding clock (ECK). Typically X’tal oscillation is used as the MCK VCXO.
  • Page 200 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Internal phase comparison The CXD3172AR internally compares the phases of the ECK-DHD signal with the frequency-divided encoding clock (ECK), against the MCK-HD signal with the frequency-divided MCK. The phase comparison result is output through PCOMP (pin 42).

  • Page 201: Line Lock Mode (Ll)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.4. Line lock mode (LL) Line lock mode is a type of external synchronization in which the camera’s vertical phase is synchronized to the AC power supply. The power supply frequency is 60Hz for NTSC and 50Hz for PAL.
  • Page 202 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 The system configuration is shown in Fig 12.2-5. Table 12.2-14 presents the external input signals. X'tal VCO(LC) (27.000MHz) (V-PLL) CXD3172AR 3.3V ACIN+ WAVE 3.3 V amplitude FORMER ACIN- digital signal Fig 12.2-5 Line lock mode Table 12.2-14 External input signals (Line lock mode)
  • Page 203 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Internal phase comparison The CXD3172AR internally compares the phases of the external power supply square wave signal (S0 pin 44 input), and the VD (MCK-VD) signal obtained by frequency-dividing the MCK (pin 43). The phase comparison result is output through PCOMP (pin 42).
  • Page 204 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Application circuit example Following is an example application involving an external rectangular wave pulse forming circuit (WAVE FORMER), LPF (V-PLL), and VCO circuit, which are required to configure external synchronization (line lock) with the SS-HQ1 system.

  • Page 205: Combined Use Of Int And Ll Modes In A Single System

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.5. Combined Use of INT and LL Modes in a Single System To switch between INT (internal) and LL (line lock) in a single set, we recommend the three switching systems presented below.
  • Page 206 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 System Switching Parameters With the “ECK-28MHz INT / ECK-27MHz LL Switching System (automatic/manual setting system)”, the CXD3172AR’s operation mode (MODESEL) must also be switched to match the input ECK frequency. In addition, with the “ECK-28MHz INT / ECK-27MHz LL Switching System (automatic/manual setting system)”, auto mode cannot be used.
  • Page 207 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 *3. SYSSELFLG SYSSELFLG is a detection flag used when the system is switched. The MODESEL and SGMODE values are switched based on the value in this parameter. SYSSELFLG is assigned to a port driver in order to use this parameter. The parameter value changes according to whether the port input signal from the exterior is “High”...
  • Page 208 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 YDLY switching control parameters With the “ECK-28MHz INT / ECK-27MHz LL Switching System (automatic/manual setting system)”, ECK is switched. For this reason, there is a possibility that the Y delay for ECK-28MHz will be different from the Y delay for ECK-27MHz in YC separate output (DACMODE=1[h]).
  • Page 209 (for 760H NTSC system configured using Sony evaluation board) The following procedure is used for YDLY switching (assumes DACMODE=1[h]) using the ECK-28MHz (MODESEL=6[h] and ECK-27MHz (MODESEL=8[h]) systems respectively, on the Sony evaluation board. 1. Set YDLY0 to “1[h]” as the ECK-28MHz setting. (See Table 12.2-23.) 2.
  • Page 210 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 ECK-27MHz INT / ECK-27MHz LL Switching System (automatic setting) With this system, ECK input is always operated at 27MHz, regardless of whether INT or LL is used. A block diagram of this system is shown in Fig 12.2-13. ATMODEON is set to 1[h] in advance (see Table 12.2-1). In addition, HVPLL (see Table 12.2-8) is assigned to a port (Pn1 in the diagram), and the port driver is set so that...
  • Page 211 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 ECK-28MHz INT / ECK-27MHz LL Switching System (manual setting) This system switches between LL and INT depending on whether the DIP switch is set to “High” or “Low”. INT mode operates with 28MHz ECK input. LL mode uses 27MHz ECK input.
  • Page 212 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 ECK-28MHz INT / ECK-27MHz LL Switching System (automatic setting) This system uses an external circuit to detect the presence or absence of external VD input, and switches between LL and INT automatically. INT mode operates with 28MHz ECK input. LL mode uses 27MHz ECK input.
  • Page 213 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 • VD Detection Circuit There is no particular external VD detection circuit which is recommended by Sony. Build a detection circuit based on the system switching timings shown below. CXD3172AR XRST...
  • Page 214 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 2. Timing for switch from LL to INT when external VD input is no longer detected (INTSW input =High) For a fixed period of time (1VD period or longer), Ext-VD presence/absence detection is performed. If Ext-VD absence is detected, “RESET output”...
  • Page 215 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 4. Timing for switch from LL to INT with external VD input (INTSW input : High => Low) When “INTSW input” switches from High to Low, “RESET output” is switched from High to Low and the CXD3172AR is reset regardless of whether Ext-VD is present or absent.

  • Page 216: Vs Lock Mode (Vsl)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.6. VS Lock Mode (VSL) In this mode, the camera’s vertical and horizontal phases are synchronized to an external video signal. The reset operation is performed in the vertical direction, and the PLL operation is performed in the horizontal direction.
  • Page 217 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Internal phase comparison The separated horizontal direction signal (EXT-HD) and the MCK-frequency-divided HD (MCK-HD) signal are phase-compared inside the CXD3172AR, and the result of the comparison is output through PCOMP (pin 42).

  • Page 218: Using The Internal Syncsep

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Applied circuit example The figure shows an example of an LPF applied circuit. Also refer to the figure below for the DC bias supply from EXVIDEO (pin 58) to EXVIDEOY (pin 57). The constant is a value used on our evaluation board. Treat it as a reference value.

  • Page 219: Vs Lock Mode (Vsl-S)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.8. VS Lock Mode (VSL-S) VS Lock (VSL-S) synchronizes the camera vertical and horizontal phases to the external VD/HD signal. A reset operation is performed in the vertical direction, and a PLL operation is performed in the horizontal direction.
  • Page 220 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Internal phase comparison The EXT-HD signal and the MCK-frequency-divided HD (MCK-HD) signal are phase-compared inside the CXD3172AR, and the result of the comparison is output through PCOMP (pin 42). The PCOMP signal is applied to the LPF (H-PLL) and fed back to the VCXO circuit on the MCK side to form the horizontal direction PLL.

  • Page 221: Vs Lock Mode (Vsl-D)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.9. VS Lock Mode (VSL-D) VS Lock (VSL-D) synchronizes the camera vertical and horizontal phases to the external digital sync signal. A reset operation is performed in the vertical direction, and a PLL operation is performed in the horizontal direction.
  • Page 222 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Internal phase comparison The result of the phase comparison is output through PCOMP (pin 42). The PCOMP signal is applied to the LPF (H-PLL) and fed back to the VCXO circuit on the MCK side to form the horizontal direction PLL. The polarity of the PCOMP signal may be switched using PCMPINV (CAT7_Byte2_bit4).

  • Page 223: Vbs Lock Mode (Vbslhp)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.10. VBS Lock Mode (VBSLHP) VBS Lock (VBSLHP) synchronizes the camera vertical, horizontal, and subcarrier phases to the external video signal. A reset operation is performed in the vertical direction, and a PLL operation is performed in the horizontal direction and on the subcarrier.
  • Page 224 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.2-27 External Input Signal (VBS Lock (VBSLHP) Mode) Pin Name(Pin No) I/O signals S0(44pin) Connected (3.3V) power supply S3(48pin) FSC signal EXVIDEOY(57pin) EXT-VIDEO-Y(1Vpp: Analog signal) EXVIDEO(58pin) EXT-VIDEO(1Vpp: Analog signal) The external video signal input to EXVIDEOY should be passed through the LPF to remove the subcarrier component.
  • Page 225 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 [TRIGGER] EXT-VIDEO EXVIDEOY input PCOMP output PCOMP Waveforms　Instability Ch1:500mV / DIV Ch2:1.00V / DIV 20.0us / DIV Fig 12.2-34 PCOMP output waveform (unlocked) • FSC phase comparison The burst component of EXT-VIDEO, which is input to EXTVIDEO (pin 58) from SYNCSEP inside the CXD3172AR, is amplified and digitized, and the resulting signal is phase-compared against the FSC signal.

  • Page 226: Vbs Lock Mode (Vbslhr)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.11. VBS Lock Mode (VBSLHR) VBS Lock (VBSLHR) synchronizes the camera vertical, horizontal, and subcarrier phases to the external video signal. A reset operation is performed in the vertical and horizontal directions, and a PLL operation is performed on the subcarrier.
  • Page 227 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.2-28 External Input Signal (VBS Lock (VBSLHR) Mode) Pin Name(Pin No) I/O signals S0(44pin) Connected (3.3V) power supply S3(48pin) FSC signal EXVIDEOY(57pin) EXT-VIDEO-Y(1Vpp: Analog signal) EXVIDEO(58pin) EXT-VIDEO(1Vpp: Analog signal) The external video signal input to EXVIDEOY should be passed through the LPF. This serves to remove the subcarrier component, and is a countermeasure against noise in cases where no external video signal is input.

  • Page 228: Reset H Reset Mode (Vrhr)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.12. V Reset H Reset Mode (VRHR) V Reset H Reset Mode synchronizes the camera vertical, horizontal, and LALT (PAL) phases to the external EXT-VD, EXT-HD, and EXT-LALT (PAL) reset signals.
  • Page 229 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 X'tal EXT-CLK CXD3172AR 3.3V EXT-LALT EXT-HD EXT-VD Fig 12.2-37 V Reset H Reset Mode (2-clock MCK-PLL) Table 12.2-29 External Input Signal (V Reset H Reset Mode) Pin Name(Pin No) I/O signals S0(44pin) EXT-VD(3.3Vpp: Digital signal)

  • Page 230: I/O Pin Initial Settings And Preventive Measures

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.13. I/O pin initial settings and preventive measures CXD3172AR pins S0-S3 (pins 44, 46, 47, and 48) are parameter-controlled I/O pins (Bi-Directional pins). In external synchronization mode, these pins are used for external synchronization input. However, during initialization (XRST removed ->...

  • Page 231: Phase Adjustment Using The Shifter

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.2.14. Phase Adjustment Using the Shifter SFTV and SFTH in Table 12.2-32 are parameters which are controlled using the keys (SFTUP, SFTDWN) for phase adjustment. The particular parameters which can be controlled differ depending on the external synchronization mode.
  • Page 232 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Parameters not controlled by keys Table 12.2-35 shows the SFTV and SFTH parameters which are not controlled by keys in the various synchronization modes. To change SFTV and SFTH that are not controlled by keys, set the parameters in Table 12.2-36.

  • Page 233: Key Operations (Shifter)

    Ver.1.0.0 January 7, 2005 12.3. Key Operations (Shifter) SS-HQ1 key operations (shifter) are used for both manual WB gain adjustment (MWB) in the WB function, and phase adjustment (SG shifter) in external synchronization. Key operations are used through external switches in combination with the port driver function.
  • Page 234 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 SFTUP/SFTDWN key arrangement Key operations can be arranged using the parameters in Table 12.3-3. This key operation provides two periods with different processing intervals. The period immediately after key release is called the initial period. The other period is called the continuous period.

  • Page 235: External Synchronization Phase Adjustment Through Key Operations

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.3.3. External Synchronization Phase Adjustment through Key Operations External synchronization phase adjustment can be performed through key operations. Parameters controlled through keys During external synchronization phase adjustment, the parameters controlled through key operations (SFTUP/SFTDWN) are SFTV and SFTH in “Table 12.2-32 Parameters Controlled by Key Operations“.

  • Page 236: Wb Gain Adjustment Through Key Operations

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.3.4. WB Gain Adjustment through Key Operations The manual white balance (MWB) gain can be adjusted through key operations. Parameters controlled through keys In MWB mode, the parameters controlled through key operations (SFTUP/SFTDWN) are WBR and WBB in Table 12.3-7.

  • Page 237: When Using The External Microcomputer

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.4. When Using the External Microcomputer 12.4.1. External Microcomputer-SS-HQ1 System Interface System Composition (Connection of External Microcomputer, DSP, and EEPROM) Even if EEPROM is available for use with an external microcomputer, it cannot be used for reading and writing in DSP (CXD3172AR) parameters via serial communication with the external microcomputer.

  • Page 238: Communication Protocol With External Microcomputers

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Note "L" and "H" of SIFSEL are recognized only during initial operation. If they are changed, be sure to reset the system. 12.4.2. Communication Protocol with External Microcomputers Communication Speed Keep the transfer rate at 400 kbps or less (1SCK > 2.5[us]).
  • Page 239 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Transmission Command Specification (External Microcomputer -> DSP) Table 12.4-2 Transmission Command Specification for Communication with External Microcomputers Communication format (in bytes) Function 6-32 Specify and read BYTEn STBN register category 01h-1Fh...
  • Page 240 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Reception Command Specification (DSP -> External Microcomputer) Table 12.4-3 Reception Command Specification for Communication with External Microcomputers Function Communication format (in bytes) 4-32 Specify and read BYTEn+1 Read data (the specified amount)
  • Page 241 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Communication format The communication format supports packets up to 32 bytes. (The size varies depending on the command.) The CXD3172AR receives a packet of data, analyzes it, and then performs control by executing a command.
  • Page 242 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Serial Data Latch and Incorporation of Data Command Command latch latch Commands reflect on parameters at the next VD latch Fig 12.4-5 Serial Data Latch and Parameter Incorporate Timing Commands are latched and executed after packets are complete (XCS="H"). However, parameter updates from register WRITE commands occur after VD latching of the next field.
  • Page 243 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Serial Communication Prohibited Period (Register Read/Write, EEPROM Read) +2HD prohibit period 2 Packet 1 Packet 2 Packet 3 (next FLD) sending sending prohibit prohibit period 2 period 3 Fig 12.4-7 Communication Prohibited Period during Register Read/Write or EEPROM Read...
  • Page 244 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Serial Communication Prohibited Period (EEPROM Write) Next EEPROM command write sending sending DSP-EEPROM access time prohibit period 4 Fig 12.4-8 Communication Prohibited Period of EEPROM Write Commands When EEPROM write command is received, the next command cannot be received more than 18 fields until the EEPROM write is complete.

  • Page 245: Pattern Generator (Pg)

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.5. Pattern Generator (PG) 12.5.1. Pattern generator (PG) Usage Method The CXD3172AR incorporates a pattern generator (PG) for applications which allows various types of patterns to be output based on the serial data settings.

  • Page 246: Pattern Settings

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.5.2. Pattern settings • Pattern settings The following table summarizes the patterns that can be output by the PG. The color settings for monochrome raster are shown in Table 12.5-5. Table 12.5-4...
  • Page 247 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 • Ramp addition PGRION add a ramp to the selected PG pattern. Table 12.5-6 Pattern settings (with ramp added) Parameter Setting Value Pattern 0[h] Displays the PG selected by PGPAT Adds a ramp to and displays the PG selected...
  • Page 248 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 • H/V settings PGHV can switch the selected PG pattern display between the horizontal and vertical directions. Table 12.5-7 Pattern settings (H/V settings) Parameter Setting Value Pattern Displays the PG selected by PGPAT in the...
  • Page 249 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 • PGRAWMIX settings PGRAWMIX can divide the display between a PG area and an imaging area, as shown below. Table 12.5-8 Pattern settings (PGRAWMIX settings) Parameter Setting value Pattern 0[h] No imaging area (only PG is output)

  • Page 250: Sync Signal Output Setting Method

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.6. Sync Signal Output Setting Method The tables below describe the parameters related to output switching for the sync signal output pins S0 (CXD3172AR 44pin), S1 (CXD3172AR 46pin), S2 (CXD3172AR 47pin), S3 (CXD3172AR 48pin), S4 (CXD3172AR 49pin).
  • Page 251 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.6-3 S2SEL S2SEL S2 pin SELect Parameter category CAT1_Byte8_bit0-2 (3bit) Outline Selects the S1 pin output signal Setting range 0[h] - 7[h] Initial value 0[h]: FSC comparison output Each signal is output according to the following settings.

  • Page 252: Adjust Output

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 12.7. ADJUST Output 12.7.1. ADJUST Function The ADJUST function is a function which performs 10-bit digital value sampling immediately after the A/D converter; performs 9-bit digital value sampling after YC processing (immediately before encoder processing);...
  • Page 253 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Table 12.7-2 ADJUST Output Data Parameter Description CAT22_Byte2_bit0-7 AJSTOUTL/M AD sampling data output CAT22_Byte3_bit0-1 CAT22_Byte54_bit0-7 YOUTL/M Y sampling data output CAT22_Byte57_bit0 CAT22_Byte55_bit0-7 RYOUTL/M R-Y sampling data output CAT22_Byte57_bit1 CAT22_Byte56_bit0-7 BYOUTL/M B-Y sampling data output...

  • Page 254: Appendix

    13.2. Operation Mode Control during Digital Output Only a limited number of operation mode (MODESEL) and external synchronization mode (SGMODE) settings can be used during digital output from the SS-HQ1. Digital output under settings other than those in the following table is not supported.

  • Page 255: Tables: The Parameters Controlled By Fw

    - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 13.3. Tables: The parameters controlled by FW CAT1 SYSTEM Byte, bit Parameter FW control timing Control methods (Except CPUHOLD=1) Byte1_bit0 NTPAL These parameters are controlled by MODESEL.. Reset Byte1_bit2 CCDTYPE Please do not change parameters controlled by FW.
  • Page 256 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Byte49 RYGAIN4 CRGAINCTL(CAT12_Byte8_bit2)=1[h] Byte50 BYGAIN4 Byte51 RYHUE4 HUECTL(CAT12_Byte8_bit4)=1[h] Byte52 BYHUE4 AWBHOLD(CAT12_Byte5_bit1)=1[h] Byte54_bit0 6DBDWN The setting value of U6DBDWN is reflected, when AWBHOLD is 1[h] and CRLESS_ON(CAT12_Byte11_bit0) is 1[h]. Byte55 BLACKS1 CLMPHOLD(CAT12_Byte5_bit3)=1[h]...
  • Page 257 - SS-HQ1 Application Notes - Ver.1.0.0 January 7, 2005 Byte1_bit4 VRSTON Byte1_bit5 BCMPON Byte1_bit6 INT60 These parameters are controlled by MODESEL. Byte1_bit7 SG27 Reset Please do not change parameters controlled by FW. Byte3 SFTHL Byte4 SFTVL Every field SGHOLD(CAT12_Byte5_bit4)=1[h] Byte5_bit0,1...
  • Page 258 Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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