Cbus Clk Interface; Dbus Clk Interface - Nokia RH-66 Troubleshooting Manual

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CBUS Clk Interface

A 1.2 MHz clock signal is used for CBUS, which is used by the MCU to transfer data
between the UEMC and the UPP.

DBUS Clk Interface

A 9.6 MHz clock signal is used for DBUS, which is used by the DSP to transfer data
between the UEMC and UPP.
The system clock is stopped during sleep mode by disabling the VCTCXO power supply
(VR3) from the UEMC regulator output by turning off the controlled output signal SleepX
from the UPP.
Issue 1 03/2005
Figure 6: CBUS data transfer
Figure 7: DBUS data transferring
©2005 Nokia Corporation
2115i/2116/2116i (RH-66)
Baseband Description and Troubleshooting
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