LG LW1100AP Manual page 5

provides the optimum bias current temperature compensation when low TC external resistors are
used. To get the best performance from the HFA3983, the output stage matching network can be
tailored using external components.
2.4 2.4GHz RF/IF Converter and Synthesizer(HFA3683)
The HFA3683A is a monolithic SiGe half duplex RF/IF transceiver designed to operate in the 2.4GHz
ISM band. The receive chain features a low noise, gain selectable amplifier (LNA) followed by a
down-converter mixer. An up-converter mixer and a high performance preamplifier compose the
transmit chain. The remaining circuitry comprises a high frequency Phase Locked Loop (PLL)
synthesizer with a three wire programmable interface for local oscillator applications. A reduced filter
count is realized by multiplexing the receive and transmit IF paths and by sharing a common
differential matching network.
2.5 I/Q Modulator/Demodulator and Synthesizer(HFA3783)
The HFA3783 is a highly integrated and fully differential SiGe baseband converter for half duplex
wireless applications. It features all the necessary blocks for quadrature modulation and
demodulation of "I" and "Q" baseband signals.
It has an integrated AGC receive IF amplifier with frequency response to 600MHz. The AGC has
70dB of voltage gain and better than 70dB of gain control range. The transmit output also features
gain control with 70dB of range.
The receive and transmit IF paths can share a common differential matching network to reduce the
filter component count required for single IF half duplex transceivers. A pair of 2nd order antialiasing
filters with an integrated DC offset cancellation architecture is included in the receive chain for
baseband operation down to DC. In addition, an IF level detector is included in the AGC chain for
threshold comparison. Up and down conversion are performed by doubly balanced mixers for "I" and
"Q" IF processing. These converters are driven by a broadband quadrature LO generator with
frequency of operation phase locked by an internal 3 wire interface synthesizer and PLL.
In the transmit path, DC coupled dual single end to differential baseband buffers have been added to
the design to help interface the device with standard single end ground referenced source equipment.
The differential buffer also applies the required common mode voltage (VREF) superimposed to the
desired signal input to each one of the differential baseband inputs. In addition, a set of jumper pins
(TX±, TX±) have also been added to permit direct monitoring of the differential stimulus/ DC
differential offset or application of external baseband signals bypassing the evaluation board buffers.
An output differential offset null capability is included and can be adjusted to zero for DC offset or to
generate adjustable differential DC levels for carrier generation (vector modulation).
The 2XLO local oscillator generation is done by an on board 748MHz VCO. The PLL set for a loop
bandwidth of 1kHz at 25? m A. Its output can be monitored thru an on board loss pad for phase noise
and spurious responses when switching from transmit to receive mode. The monitor port can also be