CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-6. External Memory Read Timing
(a) No wait (PW1, PW0 = 0, 0) setting
ASTB
RD
Lower address
Read data
AD0 to AD7
Higher address
A8 to A15
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB
RD
AD0 to AD7
Lower address
Read data
A8 to A15
Higher address
Internal wait signal
*
(1-clock wait)
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB
RD
AD0 to AD7
Lower address
Read data
A8 to A15
Higher address
WAIT
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User's Manual U15947EJ2V0UD