Rf Signal Processing Block - Sony DVP-M35 Operation Manual

2-3. RF Signal Processing Block

The block is composed of the IC806 ARP (CXD1865R) and IC810 4Mbit DRAM (pPD424260)
of the MB-78 board.
In the case of the DVD, the ARP is input with the AGC and RF equalize-processed DVD-RF
signal at the ICOO analog front end (SSI33P3720) of the TK-47 board. In the case of the CD-
DA and video-CD, it is input with the CD-RF signal from ICOO of the TK-47 board.
In the ARP, first RF signal processing such as asymmetry correction, adaptive equalization, and
sync clock extraction by the RF-PLL are carried out so that the signal becomes binary data
synchronized with the PLL clock. This data is EFMPlus demodulated (DVD)/EFM demodulated
(CD-DA and video-CD) in the demodulator, subjected to frame/sector sync detection, address
detection, and protection, and sent to the buffer memory controller.
In the case of the DVD and video-CD, the ARP is linked to the ECC core, built-in and external
memories, and output controller to carry out error correction, descrambling, EDC detection,
navigation information detection (DVD only), and output data flow control, etc. The data output
in this way is then sent to the decrypt block in the next stage.
This is the same for the CDDA. The ARP is linked to the built-in and external memories, and
CDDA signal processing block to carry out error correction, output data flow control, etc. The
signal is then muted and corrected by the CDDA signal processing block, and then sent to the
For all of these disks, RF jitter is calculated by the RF signal processing block, and this
information is used for adaptive control of the servo DSP via the CPU.
ARP
MDO-15
MAO-8
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DECRYPT
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Figure 2-9. MB-78 board RF processor, decrypt
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