Sony SAT-W60 Service Manual page 15

8 7
D
MISC_IO (10)
A U D _ V C C
A U D _ V C C
AUD_LINEIN_R
AUD_LINEOUT_L
C AUD_LINEOUT_R
AUD_LINEOUT2_L
AUD_LINEOUT2_R
A U D _ M O N O _ S W
A U D _ M O N O _ S W 2
AUD_MIC_SENSE
VID_COMP_IN AUD_MIC_SEL_OUT_N
VID_COMP_IN
VID_Y_IN
VID_Y_IN
VID_C_IN
VID_C_IN
SVID_IN_SENSE_N VID_COMP_OUT
G P I O < 2 >
VID_COMP2_OUT
SVID_SENSE_N
VID_COMP2_IN
VID_COMP2_IN
AUD_LINEIN2_L
AUD_LINEIN2_L
AUD_LINEIN2_R
AUD_LINEIN2_R
UART_CTS_DB9
UART_CTS_DB9
UART_RTS_DB9
UART_RTS_DB9
U A R T _ R X D _ D B 9
U A R T _ R X D _ D B 9
UART_TXD_DB9
UART_TXD_DB9
B
S M C _ R E S E T _ N
SMC_INSERT_N
S M C _ P W R E N A B _ N
SC_CLKDIV<0>
SC_CLKDIV<1>
IR_LED_SENSE
MODEM (6)
A
D A A _ H O O K S W _ N
DAA_LSTAT
D A A _ S N O O P _ N
DAA_RING_DET
M O D _ S M _ L R C L K
MOD_SM_BITCLK
M O D _ S M _ C L K
M O D _ S M _ X M T D A T
M O D _ S M _ R E C D A T
MOD_INT
M O D _ R E S E T
SYS_RESET_N
8 7
6
CPU (3)
FUD_INT_N
CPU_AD<31..0>
CPU_CMD<8..0>
CPU_VALIDOUT_N
C P U _ M O D E C L K
C P U _ M O D E I N
C P U _ E X T R Q S T _ N
C P U _ R E L E A S E _ N
CPU_VALIDIN_N
C P U _ V C C O K
CPU_INT_N
C P U _ C R E S E T _ N
CPU_EVALI_N C P U _ S R E S E T _ N
CPU_EVALI_N
C P U _ E V A L O _ N C P U _ W R R D Y _ N
C P U _ E V A L O _ N
C P U _ E W R R D Y _ N DIAG_INT_N
C P U _ E W R R D Y _ N
C P U _ C L K
P O W E R _ O K
SYS_RESET_N
AUD_LINEIN_L
AUD_LINEIN_L
AUD_LINEIN_R AUD_BITCLK
AUD_LINEOUT_L A U D _ C L K
AUD_LINEOUT_R AUD_LRCLK
AUD_LINEOUT2_L AUD_SDATA
AUD_LINEOUT2_R AUD_SDATAIN
AUD_MIC_IN SPD_SDATA
AUD_MIC_IN
A U D _ M O N O _ S W CPU_AD<31..0>
A U D _ M O N O _ S W 2 CPU_CMD<8..0>
AUD_MIC_SENSE C P U _ C R E S E T _ N
AUD_MIC_SEL_OUT_N CPU_INT_N
SPD_SDATA C P U _ M O D E C L K
SPD_SDATA
C P U _ M O D E I N
VID_COMP_OUT C P U _ S R E S E T _ N
VID_COMP2_OUT CPU_VALIN_N
VID_Y_OUT C P U _ V A L O U T _ N
VID_Y_OUT
VID_C_OUT CPU_EVALI_N
VID_C_OUT
G P I O < 9 > C P U _ E V A L O _ N
C P U _ E W R R D Y _ N
UART_CTS_N C P U _ V C C O K
UART_CTS_N
U A R T _ D C D _ N C P U _ W R R D Y _ N
U A R T _ D C D _ N
UART_DTR_N
UART_DTR_N
UART_RTS_N
UART_RTS_N
UART_RXD
UART_RXD
UART_TXD D A C _ C O M P A O U T
UART_TXD
D A C _ C R C B A O U T
S M C _ C L K DAC_YAOUT
S M C _ C L K
SMC_DATA
SMC_DATA
S M C _ R E S E T _ N
SMC_INSERT_N
SMC_FIT DIV_BCLK
SMC_FIT
S M C _ P E N _ N DIV_DATA<7..0>
F U D _ G P I O < 6 > DIV_HS
F U D _ G P I O < 7 > DIV_LLC
DIV_LRCLK
A U D _ C L K DIV_SDATA
PIC_CLK
IR_CLK DIV_VS
PIC_IR_CLK
GPIO<19..0>
IR_OUT ID_DATA
IR_XMT
IR_IN IIC_CLK
IR_REC
GPIO<15> IIC_DATA
IR_CLK
MISC_LED<0>
LED_DISP<0>
IR_OUT
MC1_ADDR<10..0>
M C 1 _ B S
M C 1 _ C A S _ N
M C 1 _ C K E
MC1_CS_N<1..0>
MC1_DATA<31..0>
GPIO<14> MC1_DQM<3..0>
G P I O < 4 > M C 1 _ R A S _ N
G P I O < 5 > M C 1 _ W E _ N
G P I O < 6 > MC0_ADDR<10..0>
M C 0 _ B S
M O D _ L R C L K M C 0 _ C A S _ N
MOD_BITCLK M C 0 _ C K E
M O D _ C L K MC0_CS_N<1..0>
M O D _ S D A T A MC0_DATA<31..0>
MOD_SDATAIN MC0_DQM<3..0>
M C 0 _ R A S _ N
RIO_DINT<0> M C 0 _ W E _ N
GPIO<14>
SYS_5VRESET_N
6
5 4
FUD_INT_N
CPU_AD<31..0>
CPU_CMD<8..0>
C P U _ V A L O U T _ N
C P U _ M O D E C L K
C P U _ M O D E I N
CPU_EXTRQST_N
CPU_RELEASE_N
CPU_VALIN_N
C P U _ V C C O K
CPU_INT_N
C P U _ C R E S E T _ N
C P U _ S R E S E T _ N RIO_ADDR<21..0>
C P U _ W R R D Y _ N RIO_DATA<15..0>
DIAG_INT_N RIO_CE_N<3..2>
RIO_OE_N
RIO_WE_N
C P U _ C L K
S Y S _ P W R O K SYS_RESET_N
SYS_RESET_N
AUD_BITCLK MISC_LED<2..0>
A U D _ C L K MOD_BITCLK
S O L O 2
AUD_LRCLK M O D _ C L K
AUD_SDATA M O D _ L R C L K
(2)
AUD_SDATAIN M O D _ S D A T A
SPD_SDATA MOD_SDATAIN
CPU_AD<31..0>
CPU_CMD<8..0>
C P U _ C R E S E T _ N
CPU_INT_N POT_CLK
C P U _ M O D E C L K P P _ A C K _ N
C P U _ M O D E I N P P _ A U T O F D _ N
C P U _ S R E S E T _ N P P _ B U S Y
CPU_VALIN_N PP_DATA<7..0>
C P U _ V A L O U T _ N PP_DIR
CPU_EVALI_N P P _ E R R O R
C P U _ E V A L O _ N PP_FAULT_N
C P U _ E W R R D Y _ N PP_INIT_N
C P U _ V C C O K PP_SELECT
C P U _ W R R D Y _ N PP_SELIN_N
P P _ S T R O B E _ N
RIO_ADDR<21..0>
RIO_CE_N<3..0>
D A C _ C O M P A O U T RIO_DATA<15..0>
D A C _ C R C B A O U T RIO_DEN_N<7..0>
DAC_YAOUT RIO_DEVIORDY
RIO_DINT<7..0>
RIO_DRQ<1..0>
RIO_DAK_N<1..0>
DIV_BCLK
DIV_DATA<7..0> RIO_OE_N
DIV_HS RIO_WE_N
DIV_LLC S M C _ C L K
DIV_LRCLK SMC_DATA
DIV_SDATA SMC_FIT
DIV_VS SMC_INSERT_N
GPIO<19..0> S M C _ P E N _ N
ID_DATA S M C _ R E S E T _ N
IIC_CLK SYS_2XCLKIN
IIC_DATA S Y S _ P W R O K
IR_CLK S Y S _ D P W R O K
IR_IN
IR_IN SYS_RESET_N
IR_OUT SYS_5VRESET_N
MC1_ADDR<10..0> S Y S _ R S W T C H _ N
M C 1 _ B S
M C 1 _ C A S _ N UART_CTS_N
M C 1 _ C K E U A R T _ D C D _ N
MC1_CS_N<1..0> UART_DTR_N
MC1_DATA<31..0> UART_RTS_N
MC1_DQM<3..0> UART_RXD
M C 1 _ R A S _ N UART_TXD
M C 1 _ W E _ N VID_DATA<7..0>
MC0_ADDR<10..0> VID_HSYNC_N
M C 0 _ B S VID_VSYNC_N
M C 0 _ C A S _ N
M C 0 _ C K E
MC0_CS_N<1..0>
MC0_DATA<31..0>
MC0_DQM<3..0>
M C 0 _ R A S _ N
M C 0 _ W E _ N
DRAWING
$Id: body.1.1,v 1.6 1997/05/31 14:06:45 sleat Exp $
TITLE=ELMER
A B B R E V = E L M E R
LAST_MODIFIED=Tue Mar 21 17:54:28 2000
5 4
3 2
M C 0 _ B S
MC0_ADDR<10..0>
MC0_DATA<31..0>
MC0_DQM<3..0>
M C 0 _ R A S _ N
M C 0 _ C A S _ N
M C 0 _ W E _ N
MC0_CS_N<1..0>
M C 0 _ C K E
M C 1 _ B S
MC1_ADDR<10..0>
MC1_DATA<31..0>
ROM (5)
MC1_DQM<3..0>
M C 1 _ R A S _ N
ROM_ADDR<21..0>
M C 1 _ C A S _ N
ROM_DATA<15..0>
M C 1 _ W E _ N
ROM_CE_N<3..2>
MC1_CS_N<1..0>
R O M _ O E _ N
M C 1 _ C K E
R O M _ W E _ N
MEM_CLK<3..0>
R O M _ R E S E T _ N
MISC_LED<2..0>
AUDIO (8)
MOD_BITCLK
M O D _ C L K AUD_LINEIN2_L
AUD_LINEIN2_L
M O D _ L R C L K AUD_LINEIN2_R
AUD_LINEIN2_R
M O D _ S D A T A AUD_LINEIN_L
AUD_LINEIN_L
MOD_SDATAIN
AUD_LINEIN_R
AUD_LINEIN_R
AUD_EXTIN_SEL
AUD_IN_SEL
AUD_LINEOUT_L
AUD_LINEOUT_L
VID_PIXEL_CLK AUD_LINEOUT_R
AUD_LINEOUT_R
P P _ A C K _ N AUD_LINEOUT2_L
AUD_LINEOUT2_L
P P _ A U T O F D _ N AUD_LINEOUT2_R
AUD_LINEOUT2_R
P P _ B U S Y
AUD_MIC_IN
AUD_MIC_IN
PP_DATA<7..0>
PP_DIR
A U D _ R F U
RFU_AUDIO_OUT
P P _ E R R O R AUD_TUNER_L
AUD_TUNER_L
PP_FAULT_N A U D _ T U N E R _ R
A U D _ T U N E R _ R
PP_INIT_N
PP_SELECT A U D _ C L K
A U D _ C L K
PP_SELIN_N
AUD_BITCLK
AUD_BITCLK
P P _ S T R O B E _ N
AUD_LRCLK
AUD_LRCLK
RIO_ADDR<21..0> AUD_INDATA
AUD_SDATAIN
RIO_CE_N<3..0> AUD_OUTDATA
AUD_SDATA
RIO_DATA<15..0> AUD_MIC_SEL_OUT_N
AUD_MIC_SEL_OUT_N
RIO_DEN_N<7..0> A U D _ C C L K
GPIO<12>
RIO_DEVIORDY AUD_CDATA
GPIO<13>
RIO_DINT<7..0>
A U D _ C S _ N
GPIO<10>
RIO_DRQ<1..0>
RIO_DAK_N<1..0>
A U D _ M U T E
GPIO<1>
AUD_MIC_SEL
G P I O < 3 >
RIO_OE_N A U D _ M O N O _ S W
A U D _ M O N O _ S W
RIO_WE_N A U D _ M O N O _ S W 2
A U D _ M O N O _ S W 2
S M C _ C L K
SMC_DATA
SYS_RESET_N
SYS_RESET_N
SMC_FIT
SMC_INSERT_N
S M C _ P E N _ N
S M C _ R E S E T _ N
SYS_2XCLKIN
S Y S _ P W R O K
S Y S _ D P W R O K
DAC_YAOUT
SYS_RESET_N
D A C _ C R C B A O U T
SYS_5VRESET_N
D A C _ C O M P A O U T
S Y S _ R S W T C H _ N
UART_CTS_N
U A R T _ D C D _ N
VID_Y_OUT
UART_DTR_N
VID_C_OUT
UART_RTS_N
VID_COMP_OUT
UART_RXD
VID_COMP2_OUT
UART_TXD
VID_COMP_RFU
VID_DATA<7..0>
VID_HSYNC_N
VID_VSYNC_N
C WEBTV NETWORKS, INC. 1999
This document contains privileged or otherwise legally protected
information. Disclosure of this information to anyone other
than the recipient is not authorized. You may not read, copy,
or otherwise use this document unless you are an authorized
representative of a named recipient.
E L M E R TOP
SET: BLOCK: DATE:
ENGINEER: SLEATOR/FULLER APPROVED:
3 2
1
MEM (4)
M C 0 _ B S
MC0_ADDR<10..0>
MC0_DATA<31..0>
M C 0 _ D Q M < 3 . . 0 >
M C 0 _ R A S _ N
M C 0 _ C A S _ N
M C 0 _ W E _ N
MC0_CS_N<1..0>
D
M C 0 _ C K E
M C 1 _ B S
MC1_ADDR<10..0>
MC1_DATA<31..0>
MC1_DQM<3..0>
M C 1 _ R A S _ N
M C 1 _ C A S _ N
M C 1 _ W E _ N
MC1_CS_N<1..0>
M C 1 _ C K E
MEM_CLK<3..0>
C
A U D _ V C C
A U D _ V C C
B
VIDEO (7)
VID_DAC_Y
VID_DAC_C
VID_DAC_COMP
VID_Y_OUT
VID_C_OUT
VID_COMP2_OUT
A
VID_COMP_OUT
VID_COMP_RFU
REVISION: 0.0
B L O C K
PAGE: 1 of 3
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PVT
SET
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