Huawei MU509 Series Design Manual page 14
Lga module pcm audio design guide
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Also See for MU509 Series:
- At command interface specification (227 pages) ,
- Hardware manual (94 pages) ,
- Hardware migration manual (70 pages)
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HUAWEI LGA Module PCM Audio Design Guide
The referenced codec software configuration of TLV320AIC3204 is as follows.
Values in gray color must not be changed, while values in green color can be changed.
static reg_addr_data aic3204_software_config[]=
{
this initialization phase.
need crystal oscillator any more.
{0x04,0x07},
{0x0e,0x00},
consumption and
{0x7B,0x01},
are powered up
{0x33,0x60},
0.75V) or MICBIAS = 2.5V(CM = 0.9V)
//You can change value according to hardware design
//
//programmable gain amplifiers (PGA)
Issue 04 (2016-12-12)
//Software Reset
{0x00,0x00},
{0x01,0x01},
//Reset Codec. You should wait more than 1ms during
//Clock Setting //If you use the follows Clock Setting, you do not
//BCLK to PLL
{0x00,0x00},
// PLL Clock is CODEC_CLKIN
{0x05,0x91},
//Set PLL P and R value
{0x06,0x28},
//Set PLL J value
{0x0b,0x94},
//NDAC Divider Power Control
{0x0c,0x81},
//MDAC Divider Power Control
{0x0d,0x02},
//DAC OSR MSB Value Setting
//DAC OSR LSB Value Setting
{0x12,0xA8},
//NADC Value Setting
{0x13,0x82},
//MADC Value Setting
//audio interface DSP mode
//For Slave Mode
{0x1B,0x40},
// We suggest customers use Slave Mode.
{0x1C,0x01},
//Signal Processing Settings
{0x3C,0x01},
//Select PRB_P1 (Different Blocks means different
tone
quality) PlayBack.
{0x3D,0x01},
//Select PRB_R1 Record.
//Configure Power Supplies
{0x00,0x01},
//Select Register 1
{0x01,0x08},
//Disabled weak connection of AVDD with DVDD
{0x02,0xA1},
//LDO Configuration
{0x47,0x32},
//Analog inputs power up time is 3.1 ms
// Reference will power up in 40ms when analog blocks
//uplink Setup
// MICBIAS powered up; 10: MICBIAS = 2.075V(CM =
{0x34,0x04},
// IN3L is routed to Left MICPGA with 10k resistance
{0x36,0x40},
//IN3R is routed to Left MICPGA with 10k resistance
You can change value according to hardware design
{0x3B,0x35},
// Left MICPGA Volume Control PGA=24dB
{0x3C,0x35},
// Right MICPGA Volume Control PGA=24dB
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Copyright © Huawei Technologies Co., Ltd.
Reference Design
BCLK pin is input to PLL
14
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