Toshiba TW40F80 Technical Training Manual
  1. Manuals
  2. Brands
  3. Toshiba Manuals
  4. Projection TV
  5. TW40F80
  6. Technical training manual
Toshiba TW40F80 Technical Training Manual

Toshiba TW40F80 Technical Training Manual

N5ss chassis projection television
Hide thumbs Also See for TW40F80:
Table of Contents

Advertisement

Quick Links

Download this manual See also: Owner's Manual
TECHNICAL TRAINING MANUAL
N5SS CHASSIS
PROJECTION TELEVISION
Only the different points from the training manual "N5SS chassis" with its file
No. 026-9506 are described on this manual.
For other parts common with "N5SS chassis", please refer to the original manual
with its file No. 026-9506.
©1997 TOSHIBA AMERICA CONSUMER PRODUCTS, INC.
NATIONAL SERVICE DIVISION
TRAINING DEPARTMENT
1420-B TOSHIBA DRIVE
LEBANON, TENNESSEE 37087
PHONE: (615)449-2360
FAX: (615)444-7520
www.toshiba.com/tacp
NTDPJTV05
TW40F80

Advertisement

Table of Contents
loading

Related Manuals for Toshiba TW40F80

Summary of Contents for Toshiba TW40F80

  • Page 1 Only the different points from the training manual “N5SS chassis” with its file No. 026-9506 are described on this manual. For other parts common with “N5SS chassis”, please refer to the original manual with its file No. 026-9506. ©1997 TOSHIBA AMERICA CONSUMER PRODUCTS, INC. NATIONAL SERVICE DIVISION TRAINING DEPARTMENT 1420-B TOSHIBA DRIVE...

  • Page 2: Table Of Contents

    Contents Page 1 Contents SECTION I: OUTLINE ... 6 1. FEATURE... 6 2. MERITS OF BUS SYSTEM ... 6 3. SPECIFICATIONS... 7 4. FRONT VIEW ... 8 5. REAR VIEW ... 9 6. REMOTE CONTROL VIEW... 10 7. CHASSIS LAYOUT... 11 8.
  • Page 3 SECTION V: WAC CIRCUIT ... 37 1. OUTLINE ... 37 2. CIRCUIT OPERATION ... 37 3. BLOCK DIAGRAM ... 42 4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES ... 43 SECTION VI: DUAL CIRCUIT ... 45 1. OUTLINE ... 45 2.
  • Page 4 Contents Page 3 SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT (SIDE DPC CIRCUIT) ... 82 1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP) ... 82 2. DIODE MODULATOR CIRCUIT ... 83 3. ACTUAL CIRCUIT ... 84 SECTION XI: DIGITAL CONVERGENCE CIRCUIT ... 87 1.

  • Page 5: Section I: Outline

    16:9 we introduce to North U.S.A. markets. As the basic chassis N5SS chassis is used. The future of the model TW40F80 is the use of the N5SS chassis. This chassis introduces a new bus system, devel- oped by the PHILIPS company, called the I IIC stands for Inter-Integrated Circuit control.

  • Page 6: Specifications

    3. SPECIFICATIONS Model TW56F80 TW40F80 TP61F90 TP61F80 TP55F80 TP55F81 TP50F90 TP50F60 TP50F61 TP50F50 TP50F51 7" CRT Source Hitach Remote H/U Intell RMT Keys 52 key 2-TN Dolby Surr ProLgc Surround Dsp4Ch Cyclone Audio (W) Center +20W Rear +20W Comb-Filter 3D-Y/C...

  • Page 7: Front View

    4. FRONT VIEW Fig. 1-1 Note: [No] Owner's manual page.

  • Page 8: Rear View

    5. REAR VIEW Fig. 1-2 Fig. 1-3...

  • Page 9: Remote Control View

    6. REMOTE CONTROL VIEW Fig. 1-4 Note: [No] Owner's Manual page.

  • Page 10: Chassis Layout

    7. CHASSIS LAYOUT...

  • Page 11: Construction Of Chassis

    8. CONSTRUCTION OF CHASSIS Fig. 1-6...

  • Page 12: Section Ii: Tuner, If/Mts/S. Pro Module

    SECTION II: TUNER, IF/MTS/S. PRO MODULE 1. CIRCUIT BLOCK 1-1. Outline RF signals sent from an antenna are converted into in- termediate frequency band signals (video: 45.75 MHz, audio: 41.25 MHz) in the tuner. (Hereafter, these sig- nals are called IF signals.) The IF signals are band-limited in passing through a SAW filter.
  • Page 13 1-3. Audio Multiplex Demodulation Circuit The sound multiplex composite signal FM-detected in the PIF circuit enters pin 12 of HIC (hybrid IC) in passing through the separation adjustment VR RV2 and amplified. After the amplification, the signal is split into two: one en- ters a de-emphasis circuit, and only the main signal with the L-R signal and a SAP signal removed enters the matrix cir- cuit.
  • Page 14 1-4. A.PRO Section (Audio Processor) The S.PRO section has following functions. Woofer processing (L+R output) High band, low band, balance control Sound volume control, cyclone level control Cyclone ON/OFF All these processing are carried out according to the BUS signals sent from a microcomputer. Fig.
  • Page 15 Configuration of the audio circuit and signal flow are given in Fig. 2-4 Fig. 2-4...

  • Page 16: Pop Tuner

    2. POP TUNER Fig. 2-5 2-1. Outline The POP tuner (EL922L) consists of a tuner and an IF block integrated into one unit. The tuner receives RF signals in- duced on an antenna and develops an AFT output, video output, and audio output. The tuner has receive channels of 181 as in the tuner for the main screen and it is also controlled through the I As the IC for the IF, a PLL complete sync detection plus...

  • Page 17: Section Iii: Channel Selection Circuit

    (QA02), Main and sub U/V tuners (H001, HY01), IC for deflection distortion correction (Q302), IC for 2. OPERATION OF CHANNEL SELECTION CIRCUIT Toshiba made 8 bit microcomputer TLCS-870 series for TV receiver, TMP87CS38N-3320 is employed for QA01. With this microcomputer, each IC and circuit shown below are controlled.

  • Page 18: Microcomputer

    3. MICROCOMPUTER Microcomputer TMP87CS38N-3320 has 60k byte of ROM capacity and equipped with OSD function inside. The specification is as follow. • Type name : TMP87CS38N-3320 • ROM : 60k byte • RAM : 2k byte • Processing speed : 0.5m s (at 8MHz with Shortest com- mand) •...

  • Page 19: Microcomputer Terminal Function

    4. MICROCOMPUTER TERMINAL FUNCTION Fig. 3-2...
  • Page 20 << MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >> No. Terminal Name Function INPUT BALANCE REM OUT REMOTE CONTROL SIGNAL OUT MUTE SOUND MUTE OUT SP MUTE SPEAKER MUTE DEF POW POWER POWER ON/OFF OUT POWER LED OUTPUT SS RST STARSIGHT RESET DVD CONT DVD CONTROL SCL0...

  • Page 21: Eeprom (Qa02)

    The capacity of EEPROM is 8k bits. 6. ON SCREEN FUNCTION The OSD system of TW40F80 employs the external OSD IC (QR60, MB90091) to obtain high quality OSD. Type name is 24LC08BI/P or ST24C08CB6, and those are the same in pin allocation and function, and are exchange- able each other.

  • Page 22: System Block Diagram

    7. SYSTEM BLOCK DIAGRAM Fig. 3-5...

  • Page 23: Local Key Detection Method

    8. LOCAL KEY DETECTION METHOD Fig. 3-6 Local key assignment Key No. SA-02 SA-03 SA-04 SA-05 SA-06 SA-07 SA-08 Local key detection in the N5SS chassis is carried out by using analog like method which detects a voltage appears at local key input terminals (pins 17 and 18) of the microcom- puter when a key is pushed.

  • Page 24: Remote Control Code Assignment

    9. REMOTE CONTROL CODE ASSIGNMENT Custom codes are 40-BFH (TV set for North U.S.A.) Applicable Code Function to remote control 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 6 Channel 8 Channel 8 Channel 100 Channel ANT 1/2 RESET...
  • Page 25 Custom codes are 40-BFH (TV set for North U.S.A.) Code Function SUB-BRIGHT ADJUSTMENT G. DRIVE ADJUSTMENT B. DRIVE ADJUSTMENT CUTOFF DRIVE 40H INITIALIZING, HORIZONTAL ONE LINE R. CUTOFF ADJUSTMENT G. CUTOFF ADJUSTMENT B. CUTOFF ADJUSTMENT MEMORY ALL AREA INITIALIZE PIP BRIGHT ADJUSTMENT AAH SUB CONTRAST ADJUSTMENT ABH HOR, VER PICTURE POSITON ADJUSTMENT ACH SUB COLOR ADJUSTMENT...
  • Page 26 9-1. Optional Setting for Each Model MODELS CN35F90 CN35F95 CX35F70 TW56F80 TW40F80 TP61F90 TP61F80 TP55F80 TP55F81 TP50F90 TP50F60 TP50F61 • When the character generation is changed from MB90091-107 TO MB90091-108, D5 bit of OPT0 in the design data should be set to “1”.

  • Page 27: Entering To Service Mode

    10. ENTERING TO SERVICE MODE 1. PROCEDURE Press once MUTE key of remote hand unit to indicate MUTE on screen. Press again MUTE key of remote hand unit to keep pressing until the next procedure. In the status of above (2), wait for disappearing of in- dication on screen.

  • Page 28: Failure Diagnosis Procedure

    13. FAILURE DIAGNOSIS PROCEDURE Model of N5SS chassis is equipped with self diagnosis func- tion inside for trouble shooting. 13-1. Contents to be Confirmed by Customer Contents of self diagnosis A. DISPLAY OF FAILURE INFORMATION IN NO PICTURE (Condition of display) When power protection circuit operates;...
  • Page 29 13-4. Understanding Self Diagnosis Indication In case that phenomenon always arises. See Fig. 3-7 . Item BUS LINE Detection of bus line short BUS CONT Communication state of bus line BLOCK: UV1 The sync signal part in each video signal supplied from each block is detected.
  • Page 30 13-4-1. Clearing method of self diagnosis result In the error count state of screen, press “CHANNEL DOWN” button on TV set pressing “DISPLAY” button on remote unit. CAUTION: All ways keep the following caution, in the state of service mode screen. •...

  • Page 31: Troubleshooting Chart

    14. TROUBLESHOOTING CHART 14-1. TV does Not Turned ON...
  • Page 32 14-2. No Acception of KEY-IN 14-3. No Picture (Snow Noise)
  • Page 33 14-4. Memory Circuit Check 14-5. No Indication On Screen...

  • Page 34: Section Iv: Dvd Switch Circuit

    SECTION IV: DVD SWITCH CIRCUIT 1. DVD SWITCH BLOCK DIAGRAM Fig. 4-1...

  • Page 35: Outline

    2. OUTLINE In this model, the DVD input terminals are provided in or- der to receive the color difference signals (Y, Cr, Cb) out- put from a DVD player. The luminance (Y) signal input for DVD input uses the VIDEO input terminal in common with the VIDEO 2 input. The terminals for color difference signal inputs Cr (R –...

  • Page 36: Section V: Wac Circuit

    4:3 mode and 1/2 compression process on left screen in double window mode) is performed inside the WAC unit (PB6348) in TW40F80. Screen modes for TF40F80 contain THEATER WIDE1, THE- ATER WIDE 2, THEATER WIDE3, FULL, NORMAL and DOUBLE WINDOW modes.
  • Page 37 Fig. 5-1 Wide aspect conversion unit block diagram (PB6348)
  • Page 38 • Pin Function Fig. 5-2 Pin function of TC9097F (QFP 80 pin)
  • Page 39 Table 5-1 Names and functions of TC9097F Name VRA2 VBD2 VBD4 AVDD VBD3 AGND VRD1 AVDD VBD2 AGND VBD1 AGND VFL1 AVDD RESET TST0 TST1 TST2 I color signal input – Reference voltage (low level) for AD1, AD2 Y signal input –...
  • Page 40 Name AVDD VFL2 AGND CKSEL SE42 TD14 TD13 TD12 TD11 TD10 AVDD VRA1 Ext. H sync signal input – Digital ground – Analog power Loop filter for VCO2 – – – Analog ground – – Digital power – Ext. clock input (memory write clock) Ext.

  • Page 41: Block Diagram

    Name AGND 3. BLOCK DIAGRAM – – – Bias for MPX, clamp 2 Q color signal input – Bias for AD1, AD2 – Analog ground Fig. 5-3 TC9097F system block diagram Function...

  • Page 42: Wide Aspect Conversion Circuit Failure Analysis Procedures

    4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES 4-1. Left Screen Picture Failure in Normal Mode/Double Window Modes (No Picture, Sync Distributed)
  • Page 43 4-2. Raster Horizontal One 4-2-1. Adjustment Method Disconnect any video inputs Open RX-40. Connect frequency counter to QX19 emitter. Adjust LX18 until frequency reading of “28.7 MHz ± 0.5 MHz” is obtained.

  • Page 44: Section Vi: Dual Circuit

    1. OUTLINE DUAL circuit performs the signal process, etc. on the sub screen and is composed of the followings as shown in Fig. 6- • Video/color/deflection (V/C/D) process • On-screen display (OSD) superimposing process • Sub-screen process, memory • Main/Sub screen picture superimposing process •...

  • Page 45: System Component Diagram Of Dual Unit

    3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT Fig. 6-1...

  • Page 46: Circuit Operation

    4. CIRCUIT OPERATION 4-1. Video/Color/Deflection Process Section The video/color/deflection section is shown in Fig. 6-2. The luminance signal is supplied from pin Y08 of PY01 and its frequency bandwidth is limited by the low pass filter (LPF) and then input to pin 36 of V/C/D IC (VIDEO IN). The Y signal output from pin 12 of PY01 superimposes the charac- ter signal on the video signal by QY49 and QY44, and then output to the sub screen process section.
  • Page 47 Fig. 6-2...
  • Page 48 4-2. Sub Screen Process Section The sub screen process section is shown in Fig. 6-3. The Y, I and Q signals from the video/color/deflection pro- cess section are limited in their frequency bandwidth by the LPF in the prceeding stage and input to pins 6, 13 and 15 of QY03.
  • Page 49 4-3. Main/Sub Screen Superimposing Section The main/sub screen superimposing section is shown in Fig. 6-4. The sub screen Y, I and Q signals sent from the sub screen process section and the main screen Y, I and Q signals sent from the digital unit through the receive circuit and etnered pins 3, 2, and 1 of PY02 are clamped at a same electrical potential and the former are fed to pins 1, 3, 13 and the latter...

  • Page 50: Terminal Function, Description And Block Diagram Of Main Ic

    5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF MAIN IC Fig. 6-5 QY01 m m m m m PC1832GT internal block diagram...
  • Page 51 Fig. 6-6 QY01 m m m m m PC1832GT pin layout...
  • Page 52 Fig. 6-7 QY03 TC9092AF internal block diagram...
  • Page 53 Fig. 6-8 QY03 TC9092AF pin layout...
  • Page 54 Table 6-1 QY03 TC9092AF pin list (No. 1) Pin name DAVSS DABIAS3 DABIAS2 ADVDD ADVREFY ADVSS CLAMPY ADVSS CLAMPY ADVDD ADVREFC RYIN ADBIAS BYIN ADDVDD ADDVSS NFHS OSCSI OSCSO RSTW MWD15 MWD14 MWD13 MWD12 MWD11 MWD10 MWD9 MWD8 MWD7 MWD6 MWD5 MWD4 MWD3...
  • Page 55 Table 6-2 QY03 TC9092AF pin list (No. 2) Pin name MRD1 MRD2 MRD3 MRD4 MRD5 MRD6 MRD7 MRD8 MRD9 MRD10 MRD11 MRD12 MRD13 MRD14 MRD15 RSTR CKRI YSOUT OSCMI OSCMO NFHM SDAINO PROMDI PROMCK PROMRES RESET TEST1 TESTAD DAVREFY DABIAS1 DAVDD YOUT DAVSS...
  • Page 56 Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagram Fig. 6-10 QY10/QY11 M518221-30ZS pin layout Terminal name Function SWCK Serial write clock SRCK Serial read clock Write enable Read enable Input enable Output enable RSTW Reset write RSTR Reset read Din 0 – 7 Data input Dout 0 –...

  • Page 57: Section Vii: 3-Dimension Y/C Separator Circuit

    SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT 1. OUTLINE The 3D YC separation circuit uses a comb filter with a frame memory and ideally separates the Y (luminance) and color signal for still parts of a picture, thus providing a clean pic- ture without: Dot interference causing at border areas of color pic- tures.
  • Page 58 • Terminal description (PZ01) Signal name Comb through Y-Comb C-Comb V-AV SDA1 SCL1 Fig. 7-1 3-dimension Y/C separator unit block diagram Voltage Comb through pulse for ED2 ID signal period (V frequency), 5V 2V(p-p) +9V ± 0.5V 0.6V(p-p) at burst 2V(p-p) +5V ±...

  • Page 59: Section Viii: Vertical Output Circuit

    SECTION VIII: VERTICAL OUTPUT CIRCUIT 1. OUTLINE The sync separation circuit, V pulse circuit, and blanking circuit are provided inside Q501 (TA1222AN). The saw tooth wave generation circuit and amplifier (V driver circuit) are provided inside Q302 (TA8859AP). 1-1. Theory of Operation The purpose of the V output circuit is to provide a sawtooth wave signal with good linearity in V period to the deflection yoke.

  • Page 60: Output Circuit

    2. V OUTPUT CIRCUIT 2-1. Actual Circuit 2-2. Sawtooth Waveform Generation 2-2-1. Circuit Operation The sawtooth waveform generation circuit consists of as shown in Fig. 8-4. When a trigger pulse enters pin 13, it is differentiated in the waveform shape circuit and only the falling part is detected by the trigger detection circuit, to the waveform generation circuit is not susceptible to variations of input pulse width.
  • Page 61 2-3. V Output 2-3-1. Circuit Operation The V output circuit consists of a V driver circuit Q302, Pump-up circuit and output circuit Q301, and external circuit components. Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4 output stage connected in a SEPP amplifies the cur- rent and supplies a sawtooth waveform current to a deflection yoke.
  • Page 62 To decrease the collector loss of Q3, the power supply voltage is decreased during scanning period as shown in Fig. 8-7, and VCE1 decreases and the collector loss of Q3 also decreases. Fig. 8-7 Output stage power supply voltage In this way, the circuit which switches power supply circuit during scanning period and flyback period is called a pump-up circuit.

  • Page 63: Protection Circuit For V Deflection Stop

    2-4. V Linearity Characteristic Correction 2-4-1. S-character Correction (Up-and Down-ward Extension Correction) A parabola component developed across C306 is integrated by R306 and C305, and the voltage is applied to pin 6 of Q302 to perform S-character correction. 3. PROTECTION CIRCUIT FOR V DEFLECTION STOP When the deflection current is not supplied to the deflection coils, one horizontal line appears on the screen.
  • Page 64 3-1. +35V Over Current Protection Circuit The over current protection circuit cuts off the power supply relay when it detects abnormal current increased in the +35V power line due to failure of the vertical deflection circuit. 3-1-1. Theory of Operation Fig.

  • Page 65: Raster Position Switching Circuit

    4. RASTER POSITION SWITCHING CIRCUIT 4-1. Outline When the vertical screen position adjustment is carried out on the projection TV, DC current is directly flown in the vertical deflection yoke and the raster cannot be moved up and down. (Because the raster is moved, the color distortion may occur.) Accordingly, the vertical screen position adjustment is carried out by the following method.

  • Page 66: Section Ix: Horizontal Deflection Circuit

    SECTION IX: HORIZONTAL DEFLECTION CIRCUIT 1. OUTLINE The H deflection circuit works to deflect a beam from left to right by flowing a sawtooth waveform of 15.625 kHz/15.735 kHz into the DY H deflection coil. 2. HORIZONTAL DRIVE CIRCUIT The H drive circuit works to start the H output circuit by applying H VCC (Q501 DEF power source) to pin 22 of Q501 (TA1222N) and a bias to the H drive transistor Q402 at the main power on.
  • Page 67 To shorten the storage time and the falling time, a suf- ficiently high reverse bias voltage must be applied to allow a heavy reverse current to flow. This operation also stabilizes operation of the horizontal output tran- sistor. 3-2. Circuit Description In the N5SS chassis, the off drive system is employed.

  • Page 68: Horizontal Output Circuit

    4. HORIZONTAL OUTPUT CIRCUIT The horizontal output circuit applies a 15.625 kHz/15.734 kHz sawtooth wave current to the deflection coil with mu- tual action of the horizontal output transistor and the damper diode, and deflects the electron beam from left to right in horizontal direction.
  • Page 69 Description of the basic circuit 1. t1~t2: A positive pulse is applied to base of the output transistor from the drive circuit, and a forward base current is flowing. The output transistor is turned on in sufficient saturation area. As a result, the collector voltage is almost equal to the ground voltage and the deflection current increases from zero to a value in proportionally.
  • Page 70 Amplitude Correction To vary horizontal amplitude, it is necessary to vary a sawtooth wave current flowing into the deflection coil. These are two methods to vary the current; a method which varies by connecting a variable inductance L in series with the deflection yoke, and a method which varies power supply voltage (across S-character capacitor) for the deflection yoke.
  • Page 71 Left-right Asymmetrical Correction (LIN coil) In the circuit shown in Fig. 9-9 (a), the deflection coil current iH does not flow straight as shown by a dotted line in the Fig. 9-9 (b) if the linearity coil does not exist, by flows as shown by the solid line because of effect of the diode for a first scanning (screen left side) and effect of resistance of the deflection coil for later half period of scanning (screen right side).
  • Page 72 4-2. White Peak Bending Correction Circuit 4-2-1. Outline White peak area in screen picture may sometimes cause bend- ing in picture. See figure below. In TP48E60 series, correction signal which video ripple in video output circuit power supply 200V is input to pin 24 (Bending correction terminal) of Q501.
  • Page 73 4-3. H Blanking 4-3-1. Outline The H blanking circuit applies a blanking precisely for the horizontal flyback period so that undesirable pictures fold- ing does not appear at screen ends. This unit allows the users to adjust an horizontal amplitude adjustment, so, picture quality at screen ends will be im- proved.
  • Page 74 4-4. 200V Low Voltage Protection 4-4-1. Outline When the video output power supply 200V is stopped by some abnormality occurence, the current inside CPT in- creases abnormally. So the CPT may be damaged. To pre- vents this, a 200V low voltage protection circuit is provided. 4-4-2.

  • Page 75: High Voltage Generation Circuit

    5. HIGH VOLTAGE GENERATION CIRCUIT The high voltage generation circuit develops an anode volt- age for the picture tube, focus, screen, CRT heater, video output (210V) and so on by stepping up the pulse voltage developed for flyback period of the horizontal output cir- cuit with the FBT, and supplies the power to various cir- cuit.
  • Page 76 5-1-1. +210V For the flyback period, pulses are stacked up to DC +125V with FBT, and the voltage is rectified by D406 and filtered by C446. 5-1-2. +35V, 12V Pin 4 of the FBT is grounded and the shaded area of nega- tive pulse developed for opposite period of the flyback pe- riod is rectified, thus developing better regulation power supply.

  • Page 77: High Voltage Circuit

    6. HIGH VOLTAGE CIRCUIT 6-1. High Voltage Regulator 6-1-1. Outline Generally, four kinds of methods exist to stabilize a high voltage in high voltage output circuits using the FBT: Stabilization by varying the power supply voltage. Stabilization by varying L value with a saturable reac- tance connected in series with the primary winding of the FBT.
  • Page 78 6-1-3. Actual Fig. 9-22 shows the actual circuit used in the unit. A resonant capacitor C0 is also split into two capacitors C443 and C444 in this circuit. The high voltage regulator cirucits is structured by splitting the C443 to two capacitors of C443 and C448.

  • Page 79: X-Ray Protection Circuit

    7. X-RAY PROTECTION CIRCUIT 7-1. Outline In case picture tube using high voltage, when high voltage rises abnormally due to components failure and circuit mal- function, there is possible danger that X-RAY leakage in- creases to affect human body. To prevent it, X-RAY protec- tion circuit is equipped.

  • Page 80: Over Current Protection Circuit

    8. OVER CURRENT PROTECTION CIRCUIT 8-1. Outline If main power (125V) current increases abnormally due to components failure, there is possible danger of the second- ary damage like failure getting involved in other part fail- ure, and abnormal heating. To prevent this, over current pro- tection circuit is equipped, which detects current of main B line to turn off power relay in abnormal situation.

  • Page 81: Section X: Deflection Distortion Correction Circuit

    SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT 1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP) 1-1. Outline The deflection distortion correction IC (TA8859CP), in com- bination with a V/C/D IC (TA1222AN) which has a V pulse output, performs correction for various deflection distortions and V output through the I C bus control.

  • Page 82: Diode Modulator Circuit

    2. DIODE MODULATOR CIRCUIT In N5SS, the distortion correction is carried out by the ditigal convergence circuit. So the component of the diode modu- lator circuit is the same as that of conventional television, because it is used only for the horizontal oscillation adjust- ment.

  • Page 83: Actual Circuit

    3. ACTUAL CIRCUIT In the actual circuit, the resonant capacitor is split into two as shown in Fig. 10-7. One, C440, is inserted between the collector of the H. OUT transistor and ground and another C444 inserted between the collector and emitter. In Fig. 10- 5, C440 is expressed as C and C444 as C current path for the flyback period is shown by arrows.
  • Page 84 3-1. Basic Operation and Current Path 3-1-1. Later Half Scanning Period When the power is turned on, the power supply voltage V is applied to C and Csm, and the C acts as a power source for a later half of the scanning period for which the H. OUT transistor is turned on, and the deflection current I the path as shown below.
  • Page 85 3-1-3. Later Half of Flyback Period All energy in the coil has been transferred to the resonant capacitors at the center of the flyback period, and the volt- age shows the maximum value. However, during next half of the flyback period, the energy of the resonat capacitor is discharged as a reverse current through respective coil.

  • Page 86: Section Xi: Digital Convergence Circuit

    SECTION XI: DIGITAL CONVERGENCE CIRCUIT 1. OUTLINE The digital convergence circuit develops outputs to correct screen distortion and perform color matching. The digital convergence circuit used is of an all digital type and allows good adjustments in comprise with a conventional analog type circuit.
  • Page 87 Fig. 11-1 Block diagram...

  • Page 88: Picture Adjustment

    3. PICTURE ADJUSTMENT Four screens for Normal/Full, Theater wide 1, Theater Wide 2, Theater Wide 3 are provided for the adjustments. When making the adjustments, receive the U/VHF or CABLE broadcasting signal or the built-in pattern signal of the mi- croprocessor to make a synchronization with the frequency of the adjusting screen with the unit..

  • Page 89: Service Mode

    3-2. Service Mode 3-2-1. Outline The service mode, one of the functions this unit provides, is controlled by the microprocessor QA01 and . This mode is set by the special operation to avoid the easy operation by the user. Move the cursor to between the adjust- ment points of 8*7/each color and modify the data directly.
  • Page 90 3-2-3. Initial screen The screen mode is Normal/Full screen mode. Correction point: Vertical 8 * Horizontal 7 (® and - marks are the adjusting points.) First screen: The initial cross hatch screen appears. The pattern col- ors are displayed with 3 colors. The cursor color is red and left blinking.
  • Page 91 3-2-4. Key function of remote control unit Fig. 11-5...
  • Page 92 3-2-5. Operation procedure Set the screen to Normal or Full mode using the PIC- SIZE key on the remote controller. Set the unit to the service mode with MUTE + MUTE + MENU keys pressed. (Entering to S mode.) Set the unit to the convergence adjusting mode by press- ing the “7”...
  • Page 93 3-3-2. Theater Wide1 Fig. 11-7 Fig. 11-8...
  • Page 94 3-3-3. Theater Wide 2 Fig. 11-9 Fig. 11-10...
  • Page 95 3-3-4. Theater Wide 3 Fig. 11-11 Fig. 11-12...

  • Page 96: Case Study

    4. CASE STUDY In many cases, a color deviation will be corrected by return- ing the HIT and WID data for the main deflection side to the initial values. Followings are cases which need readjustment of the conver- gence by all means. 4-1.

  • Page 97: Troubleshooting

    5. TROUBLESHOOTING 5-1. Adjusting Procedure in Replacing CRT 5-2. Adjusting Procedure in Replacing Convergence Unit/Main Def...

  • Page 98: Convergence Output Circuit

    6. CONVERGENCE OUTPUT CIRCUIT 6-1. Outline This circuit current-amplifies digital convergence correction signal at output circuit, and drives by convergence yoke to perform picture adjustment. Digital convergence output signal 6ch adjustment is done. (H-R/G/B) (V-R/G/B) 6-2. Circuit Description 6-2-1. Signal flow Signal which is corrected by digital convergence, is output to P708 (V, H R/G/B);...
  • Page 99 6-3. Convergence Block Diagram Fig. 11-14...

  • Page 100: Convergence Troubleshooting Chart

    7. CONVERGENCE TROUBLESHOOTING CHART Fig. 11-6...

  • Page 101: Overall Block Diagram

    MAIN UNIT HY01 TUNER/IF H003 S C L S D A TV2-V A T F 2 H001 H002 TUNER TUNER S C L S D A A T F 1 R W L S C L S D A Q A 0 1 M I C R O C O M P U T E R A F T 2 Y S / Y M...

Table of Contents