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Toshiba TX39 Series User Manual

Toshiba TX39 Series User Manual

32bit risc microprocessor
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Users Manual
32bit RISC Microprocessor
TX39 family
TMPR3904F
Rev.2.0
Jan. 12. 1998

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Summary of Contents for Toshiba TX39 Series

  • Page 1 Users Manual 32bit RISC Microprocessor TX39 family TMPR3904F Rev.2.0 Jan. 12. 1998...

  • Page 3: Table Of Contents

    INTRODUCTION ............................1 Overview..............................1 Notation used in this manual ........................2 Kind of accessing by the TX3904....................3 Precautions in the TMPR3904F specification ...............4 FEATURES ..............................7 CONFIGURATION............................9 PINS ................................11 Positions of Pins ...........................11 Functions of Pins .........................13 ADDRESS MAPS............................17 Memory Map ..........................17 Register Map..........................18 Chip Configuration Register .....................21 5.3.1 DMA transfer of SIO ......................21 5.3.2 PIO2 and PIO1 ........................22...
  • Page 4 7.2.2 Absence register access......................41 7.2.3 Time-out error...........................41 16-bit Bus Mode..........................43 Half Speed Bus Mode ........................45 Bus Arbitration...........................46 7.5.1 Bus ownership granted......................46 7.5.2 Release of bus ownership......................47 7.5.3 Kinds of bus ownership ......................48 7.5.4 Snoop function...........................49 Interrupts ............................50 7.6.1 INT[7:0]............................50 7.6.2 NMI*............................50 Reset..............................50 DRAM CONTROLLER (DRAMC) ......................51 Features ..............................51...
  • Page 5 8.5.12 Operations at the time of reset ....................70 Timing Diagrams ..........................71 8.6.1 32-bit bus single read operation ....................71 8.6.2 32-bit word single read operation with 16-bit bus ..............74 8.6.3 32-bit bus fast page mode read (Burst mode) ................75 8.6.4 16-bit bus fast page mode word read (Burst read) ..............75 8.6.5 32-bit bus fast page mode read (Burst read) page hit miss ............76 8.6.6 32-bit bus hyper page mode read (Burst read) ................77 8.6.7 32-bit bus hyper page mode read (Page hit miss) ..............77...
  • Page 6 9.5.8 32-bit bus page mode burst read operation (Page mode MROM) ...........106 9.5.9 16-bit bus word normal mode burst read operation (ROM/SRAM) ........107 9.5.10 16-bit bus page mode burst read (word) operation (Page mode MROM) ......108 9.5.11 32-bit bus normal mode burst write (SRAM) ................109 9.5.12 16-bit bus normal mode burst write (word) (SRAM;...
  • Page 7 11 INTERRUPTS ............................162 11.1 Features ............................162 11.2 Configuration ...........................163 11.3 Functions............................164 11.3.1 Interrupt sources ........................164 11.3.2 Interrupt detection........................165 11.3.3 Interrupt priority arbitration process..................165 11.4 Registers............................166 11.4.1 Register map ..........................166 11.4.2 Interrupt status register (ISR) ....................167 11.4.3 Interrupt level registers (ILR3-ILR0) ..................168 11.4.4 Interrupt mask register (IMR)....................169 12 SERIAL PORTS (SIO) ..........................170 12.1 Features ............................170...
  • Page 8 12.4.13 Error flag..........................189 12.4.14 Multi-controller system......................189 12.5 Timing Explanations ........................191 12.5.1 Operation at the time of receiving (7 and 8 bit data length) ..........191 12.5.2 Timing of SDMAREQ*/SMAACK* at the time of DMA I/F (at DMA level 4) ....191 12.5.3 Operation at the time of receiving (8 and 9 bit length multi-controller system; ....192 12.5.4 Operation at the time of receiving (8 and 9 bit length multi-controller system;...

  • Page 9: Introduction

    Users Manual INTRODUCTION Overview “ ” “ ” ’...

  • Page 10: Notation Used In This Manual

    Users Manual Notation used in this manual Mathematical notation Data notation Signal notation “ ” “ ”...

  • Page 11: Kind Of Accessing By The Tx3904

    Users Manual Kind of accessing by the TX3904...

  • Page 12: Precautions In The Tmpr3904F Specification

    Users Manual Precautions in the TMPR3904F specification ’ Don’t set Don’t ’ ’ ’...
  • Page 13 Users Manual ’ Do not use...
  • Page 14 Users Manual...

  • Page 15: Features

    Users Manual FEATURES...
  • Page 16 Users Manual...

  • Page 17: Configuration

    CONFIGURATION T X 3 9 p r o c e s s o r c o r e I - C a c h e R 3 9 0 0 D - C a c h e W B U D S U D e b u g I n t e r f a c e G - B u s I / F...
  • Page 18 Users Manual ’ ’...

  • Page 19: Positions Of Pins

    Users Manual PINS Positions of Pins...
  • Page 20 Users Manual...

  • Page 21: Functions Of Pins

    Users Manual Functions of Pins...
  • Page 22 Users Manual...
  • Page 23 Users Manual ’...
  • Page 24 Users Manual ’...

  • Page 25: Address Maps

    Users Manual ADDRESS MAPS Memory Map ’ V i r t u a l A d d r e s s S p a c e P h y s i c a l A d d r e s s S p a c e 0 x F F F F _ F F F F 0 x F F F F _ F F F F R e s e r v e d A r e a...

  • Page 26: Register Map

    Users Manual Register Map...
  • Page 27 Users Manual...
  • Page 28 Users Manual...

  • Page 29: Chip Configuration Register

    Users Manual Chip Configuration Register P2En P1En POBus EIClr BEOW R/W R/W R/W R/W R/W : Type : Initial Value EIM7 EIM6 EIM5 EIM4 EIM3 EIM2 EIM1 EIM0 : Type : Initial Value 5.3.1 DMA transfer of SIO ’ ’...

  • Page 30: Pio2 And Pio1

    Users Manual 5.3.2 PIO2 and PIO1...

  • Page 31: Error Processing

    Users Manual Error processing 5.3.3 Time out error Time Out Error Enable (Initial value: 0) detection 1: Enable time out error detection. 0: Disable time out error detection. BEOW Bus error Bus Error On Write occurred Indicates that a bus error was generated by a during write write operation of the TX39 processor core.

  • Page 32: Connection Of External Bus Master

    Users Manual 5.3.4 Connection of external bus master 5.3.5 INT[7:0] active status clear...

  • Page 33: Int[7:0] Active Status Set-Up

    Users Manual 5.3.6 INT[7:0] active status set-up...
  • Page 34 Users Manual...

  • Page 35: Clock

    Users Manual CLOCKS 6.1 Clock Generator The TX3904 has a built-in x4 frequency PLL clock generator. Please connect a crystal oscillator with a frequency of a quarter of the internal system clock (frequency of the TX39 Processor Core’s input clock). 6.2 Operation Modes of TX3904 The following describes the operation modes by the TX3904 clock control.

  • Page 36: Doze Mode

    Users Manual The halt bit must be set to 1 with an example flow shown below in order to make the TX3904 halt mode. An exception must be caused when the TX3904 is recovered form halt mode. An interrupt must not be masked. address instruction comment...

  • Page 37: Status Shifting

    Users Manual field is changed during a bus operation, the clock is changed without waiting for the completion of the bus operation. The RF mode lowers the power consumption by supplying clocks that correspond the RF field for the peripheral macro cell(s) and the mega cell core in the parts that are not affected by frequency changes.

  • Page 38: Operations Of Each Block In The Each Modes

    Users Manual 6.4 Operations of each block in the each modes Table 6-1 Operations of each block in the each modes Block Function Operation Operation Clock in Doze in Halt change in Mode Mode RF Mode TX39 Snoop function Operation Halts Interrupt function Operation Operation Change Others...

  • Page 39: Bus Operations

    TOSHIBA TMPR3904F Rev. 2.0 BUS OPERATIONS This chapter explains the bus operations of the TX3904: Operations for which the TX3904 built-in memory controllers are not used. Basic Bus Operations There are three kinds in the TX3904 bus operations--the single read operation, the burst read operation, and the single write operation.
  • Page 40 TOSHIBA TMPR3904F Rev. 2.0 SCS Address register CS3Addr CS2Addr : Type 0x20 0x20 : Initial Value CS1ADDr CS0Addr : Type 0x20 0x20 : Initial Value Mnemoni Name of Description Field 31:24 SCS3 SCS3* Address (initial value: 0x20) CS3Addr address Asserts a CS3 signal when the high-order 8 bits (A[31:24]) of the address (physical address) matches the CS3Addr.
  • Page 41 TOSHIBA TMPR3904F Rev. 2.0 SCS Mask register CS3Mask CS2Mask : Type 0xFF 0xFF : Initial Value CS1Mask CS0Mask : Type 0xFF 0xFF : Initial Value Mnemonic Name of Description Field 31:2 CS3Mas SCS3 SCS3* Mask (initial value: 0xFF) Specifies the valid bit of the address...
  • Page 42 TOSHIBA TMPR3904F Rev. 2.0 SCS Wait register CS316 CS3Wait CS216 CS2Wait : Type I nitial • F Value CS116 CS1Wait CS016 CS0Wait : Type : Initial Value Mnemoni Name of Description Field CS316 CS3 16 bits bits Sets up the data width of the SCS[3]* area.

  • Page 43: Single Read Operation

    TOSHIBA TMPR3904F Rev. 2.0 7.1.2 Single read operation The single read operation is a bus operation to read data of 4 bytes or less. The following diagram shows the operation of the shortest case (no wait) that has no wait cycle:...
  • Page 44 TOSHIBA TMPR3904F Rev. 2.0 Wait cycles can be entered by not asserting the ACK* signal. The following diagram shows the operation in the case of one wait: w a i t S Y S C L K A[31:1] B E [3:0]*...

  • Page 45: Burst Read Operation

    TOSHIBA TMPR3904F Rev. 2.0 7.1.3 Burst read operation The burst read operation is a bus operation to conduct refills of multiple words of the cache at a high speed. If instructions and data to be read in by the cache are in the memory that is managed by the TX3904 built-in memory controller, it is a operation to be discussed in the chapters of memory controllers (“DRAM Controller”...
  • Page 46 TOSHIBA TMPR3904F Rev. 2.0 In the case of a burst read operation also, wait cycles can be entered by not asserting the ACK* signal. The following diagram shows the operation in the case where a wait cycle is entered while the first and third data are being read.

  • Page 47: Single Write Operation

    TOSHIBA TMPR3904F Rev. 2.0 7.1.4 Single write operation The only write operation that the TX39 Processor Core supports is the single write operation. The following diagram shows the timing of the single write operation without a wait cycle (of no wait):...
  • Page 48 TOSHIBA TMPR3904F Rev. 2.0 Wait cycles can be inserted by not asserting the ACK* signal. The following diagram shows the operation in the case where a wait cycle has been inserted (one wait). w a i t S Y S C L K...

  • Page 49: Bus Error

    TOSHIBA TMPR3904F Rev. 2.0 Bus Error 7.2.1 BUSERR* signal The TX3904 employs the BUSERR* input signal. The peripheral circuits can report that problems occurred during a bus operation by asserting a BUSERR* signal. The following operation occurs with respect to the BUSERR* signal.
  • Page 50 TOSHIBA TMPR3904F Rev. 2.0 During bus operation of the TX3904 on-chip DMA controller The DMA controller immediately suspends transfer operation, then abnormally ends the channel operation. During bus operation of the external bus master The TX3904 asserts BUSERR* signal. 2 5 5...

  • Page 51: Bit Bus Mode

    TOSHIBA TMPR3904F Rev. 2.0 16-bit Bus Mode The TX3904 can control the data bus as 16-bit width bus in the memory area of the RAMC, the memory area of the ROMC, and the area of the SCSn (16-bit bus mode). The 16-bit width should be designated in the built-in register of each module as for the memory areas controlled by the RAMC or the ROMC, and in the built-in register of the EBIF as for the area of the SCSn.
  • Page 52 TOSHIBA TMPR3904F Rev. 2.0 As an example, the following diagram shows the word access in the case where the SCSn area is 16-bit bus (one wait): w a i t w a i t S Y S C L K...

  • Page 53: Half Speed Bus Mode

    TOSHIBA TMPR3904F Rev. 2.0 Half Speed Bus Mode To simplify the design of the peripheral system, the TX3904 supports the half speed bus mode that executes the bus operation at half of the operation frequency of the TX39 Processor Core. For example, when a crystal oscillator of 12.5 MHz is connected to the TX3904, the TX39 Processor Core operates at...

  • Page 54: Bus Arbitration

    TOSHIBA TMPR3904F Rev. 2.0 Bus Arbitration The TX3904 can connect a bus master externally. The arbitration of the bus ownership with an external bus master is conducted through four signals of BUSREQ*, BUSGNT*, BUSREL*, and HAVEIT*. The external bus master is to be daisy-chain connected in the downstream of the TX3904 built-in DMAC (See “10.2.1.

  • Page 55: Release Of Bus Ownership

    TOSHIBA TMPR3904F Rev. 2.0 7.5.2 Release of bus ownership The external bus master releases the bus ownership for two reasons: Because the bus ownership is no longer necessary Because of the BUSREL*. (1) Release of the bus ownership because it is no longer necessary...

  • Page 56: Kinds Of Bus Ownership

    TOSHIBA TMPR3904F Rev. 2.0 (2) Release by BUSREL* When the external bus master has the bus ownership, the TX3904 in some cases requests the release of the bus ownership by asserting the BURSEL*. The cases where the TX3904 requests the release of the bus ownership are:...

  • Page 57: Snoop Function

    TOSHIBA TMPR3904F Rev. 2.0 HPSREQ (High Priority Snoop Request) HPGREQ (High Priority General Request) SREQ (Snoop Request) GREQ (General Request) Which bus ownership of these should be used is to be set up in the POBus field of the CConR of the EBIF.

  • Page 58: Interrupts

    TOSHIBA TMPR3904F Rev. 2.0 Interrupts In the TX3904, there are eight interrupt signals (INT[7:0]) and one non- maskable interrupt signal (NMI*). 7.6.1 INT[7:0] The INT[7:0] is a signal to request for an interrupt of the TX3904. It is used when the external circuit requests an interrupt. The active status of INT[7:0] is set up in the CConR of the EBIF.

  • Page 59: Features

    TOSHIBA TMPR3904F Rev. 2.0 DRAM CONTROLLER (DRAMC) Features The signals and timings that will be necessary to control the DRAM are generated. (1) Two-channel support Up to four banks can be structured on a channel. (2) Independent timing set-up is possible for each channel...

  • Page 60: Block Diagrams

    TOSHIBA TMPR3904F Rev. 2.0 Block Diagrams The following Figure 8-1 shows the connection of the DRAMC inside the TX3904 and Figure 8-2 shows the internal blocks: TX3904 G-BUS I/F SIGNAL RAS0[3:0]* RAS1[3:0]* CAS[3:0]* G-BUS I/F DRAMC SIGNAL EBIF MA[11:0] RESET*...

  • Page 61: Registers

    TOSHIBA TMPR3904F Rev. 2.0 Registers Table 8-1 DRAMC Registers Address Register Symbol Register Name 0xFFFF_8000 DCCR0 Channel Control Register 0 0x FFFF_8004 DBMR0 Base Address Mask Register 0 0x FFFF_8008 DWR0 Wait Register 0 0x FFFF_8100 DCCR1 Channel Control Register 1...

  • Page 62: Explanations Of Registers

    TOSHIBA TMPR3904F Rev. 2.0 Explanations of Registers 8.4.1 Channel control register 0 (DCCR0) DBA0 DRA0 : Type 0x200 : Initial Value DCW0 DRP0 DCS0 DIM0 DPM0 16BUS0 : Type : Initial Value Name of Field Description Mnemonic 31:20 DBA0 DRAM channel 0...
  • Page 63 TOSHIBA TMPR3904F Rev. 2.0 Name of Field Description Mnemonic DCS0 DRAM channel 0 DRAM Control Channel Size on Channel 0 size Designates the total memory size to be assigned to all of four banks on Channel 0. 000: 1 Mbytes 100: 16 Mbytes...

  • Page 64: Base Address Mask Register 0 (Dbmr0)

    TOSHIBA TMPR3904F Rev. 2.0 8.4.2 Base address mask register 0 (DBMR0) DBAM0 : Type 0x000 : Initial Value : Type : Initial Value Mnemonic Name of Field Description 31:20 DBAM0 DRAM channel 0 DRAM Control Base Address Mask on Channel 0...

  • Page 65: Wait Register 0 (Dwr0)

    TOSHIBA TMPR3904F Rev. 2.0 8.4.3 Wait register 0 (DWR0) PWTE0 WTE0 : Type : Initial Value PWTD0 WTD0 PWTC0 WTC0 : Type : Initial Value Mnemonic Name of Field Description PWTE0 DRAM channel 0 Page Mode Wait Cycle for External Bus Master...
  • Page 66 TOSHIBA TMPR3904F Rev. 2.0 Mnemonic Name of Field Description 10:8 WTD0 DRAM channel 0 Normal Mode Wait Cycle for Internal DMAC internal DMAC Designates the number of wait cycles with normal mode wait which the internal DMAC accesses the Channel 0 DRAM in the normal mode (single mode).

  • Page 67: Channel Control Register 1 (Dccr1)

    TOSHIBA TMPR3904F Rev. 2.0 8.4.4 Channel control register 1 (DCCR1) DBA1 DRA1 : Type 0x200 : Initial Value DCW1 DRP1 DCS1 16BUS1 DIM1 DPM1 : Type : Initial Value Name of Field Description Mnemonic 31:20 DBA1 DRAM channel 1 DRAM Control Base Address on Channel 1...
  • Page 68 TOSHIBA TMPR3904F Rev. 2.0 Name of Field Description Mnemonic DCS1 DRAM channel 1 DRAM Control Channel Size on Channel 1 size Designates the total memory size to be assigned to all of four banks on Channel 1. 000: 1 Mbytes 100: 16 Mbytes...

  • Page 69: Base Address Mask Register 1 (Dbmr1)

    TOSHIBA TMPR3904F Rev. 2.0 8.4.5 Base address mask register 1 (DBMR1) DBAM1 : Type 0x000 : Initial Value : Type : Initial Value Name of Field Description Mnemonic 31:20 DBAM1 DRAM channel 1 DRAM Control Base Address Mask on Channel 1...

  • Page 70: Wait Register 1 (Dwr1)

    TOSHIBA TMPR3904F Rev. 2.0 8.4.6 Wait register 1 (DWR1) PWTE1 WTE1 : Type : Initial Value PWTD1 WTD1 PWTC1 WTC1 : Type : Initial Value Name of Field Description Mnemonic PWTE1 DRAM channel 1 Page Mode Wait Cycle for External Bus Master...
  • Page 71 TOSHIBA TMPR3904F Rev. 2.0 Name of Field Description Mnemonic 10:8 WTD1 DRAM channel 1 Normal Mode Wait Cycle for Internal DMAC internal DMAC Designates the number of wait cycles with normal mode wait which the internal DMAC accesses the Channel 1 DRAM in the normal mode (single mode).

  • Page 72: Refresh Control Register (Drefc)

    TOSHIBA TMPR3904F Rev. 2.0 8.4.7 Refresh control register (DREFC) : Type : Initial Value CBRSE DRCYC : Type 1100000000 : Initial Value Name of Field Description Mnemonic CBRSE Self refresh CBR Self Refresh Enable enable Designates whether or not to use the DRAM self- refresh function in the halt mode.

  • Page 73: Operations

    TOSHIBA TMPR3904F Rev. 2.0 Operations 8.5.1 Channel select The channel select for DRAM access is conducted by the physical address. Of the addresses, the high-order 12 bits are compared if they are within the range from the base address DBAn (n=1, 0) that is set up in the channel control register DCCRn (n=1, 0) to the size that is set up in the size register DCSn (n=1, 0), and if they are in the range, the channel is selected.

  • Page 74: Address Multiplex

    TOSHIBA TMPR3904F Rev. 2.0 Depending on the set-up of the base address and size of each channel, two channels are sometimes selected. In such a case, the channel to which a higher base address is set up is selected. When accessing the addresses shown in Figure 8-10, Channel 1 with a higher base address value is selected.

  • Page 75: Operation Modes

    TOSHIBA TMPR3904F Rev. 2.0 8.5.3 Operation modes Table 8-3 Bus Operation of Bus Master and Memory Operation Mode Memory Device Access Data Device Bus Master (CPU, DMAC) Operation Mode Type Length Single Operation Burst Operation 32-bit 16-bit 32-bit 16-bit Normal Mode...

  • Page 76: Bit Static Bus Sizing

    TOSHIBA TMPR3904F Rev. 2.0 8.5.4 32/16-bit static bus sizing Supports the DRAM of 16-bit bus width by setting up 16BUS0 and 16BUS1 of the DCCRn (n=1,0). 32-bit Bus Access Indicates that the DRAM connected to the channel is 32-bit bus when the 16BUSn of the DRAM channel control register is 0.

  • Page 77: Page Mode Support And Page Hit Detection

    TOSHIBA TMPR3904F Rev. 2.0 8.5.7 Page mode support and page hit detection The page mode of the DRAM is a method to access while keeping asserting RAS* and changing the column address under the fixed row address. In the DRAMC, when the bus master conducts the burst mode access, the page mode of the DRAM is used.

  • Page 78: Arbiter

    TOSHIBA TMPR3904F Rev. 2.0 8.5.11 Arbiter For the arbitration of the refresh and DRAM access, the request that came first has the priority. If one of them is in operation, a new request is made to wait. The refresh during a DRAM access waits until the DRAMC replys ACK* to processor core.

  • Page 79: Timing Diagrams

    TOSHIBA TMPR3904F Rev. 2.0 Timing Diagrams 8.6.1 32-bit bus single read operation (1) DRAM access by the internal bus master S i n g l e R e a d C y c l e 2 - W a i t...
  • Page 80 TOSHIBA TMPR3904F Rev. 2.0 (2) When the external bus master conducts a DRAM access (Half speed bus mode: HALF*=low) S i n g l e R e a d C y c l e W a i t ( a u t o )
  • Page 81 TOSHIBA TMPR3904F Rev. 2.0 (3) When the external bus master conducts a DRAM access (Full speed bus mode; HALF*=high) S i n g l e R e a d C y c l e W a i t ( a u t o )

  • Page 82: Bit Word Single Read Operation With 16-Bit Bus

    TOSHIBA TMPR3904F Rev. 2.0 8.6.2 32-bit word single read operation with 16-bit bus (1) Fast page DRAM 3 2 - b i t S i n g l e R e a d ( 1 6 - b i t D a t a B u s )

  • Page 83: Bit Bus Fast Page Mode Read (Burst Mode)

    TOSHIBA TMPR3904F Rev. 2.0 8.6.3 32-bit bus fast page mode read (Burst mode) N o r m a l R e a d P a g e l R e a d W a i t W a i t...

  • Page 84: Bit Bus Fast Page Mode Read (Burst Read) Page Hit Miss

    TOSHIBA TMPR3904F Rev. 2.0 8.6.5 32-bit bus fast page mode read (Burst read) page hit miss N O R M A L R E A D F A S T P A G E R E A D P A G E H I T M I S S / R E C O V E R Y...

  • Page 85: Bit Bus Hyper Page Mode Read (Burst Read)

    TOSHIBA TMPR3904F Rev. 2.0 8.6.6 32-bit bus hyper page mode read (Burst read) N O R M A L R E A D P A G E R E A D W a i t W a i t W a i t...

  • Page 86: Bit Bus Single Write (Early Write)

    TOSHIBA TMPR3904F Rev. 2.0 8.6.8 32-bit bus single write (Early write) (1) DRAM access by the internal bus master S i n g l e W r i t e C y c l e 2 W a i t...
  • Page 87 TOSHIBA TMPR3904F Rev. 2.0 (2) DRAM access by the external bus master (Half speed bus mode; HALF*=low) S i n g l e W r i t e C y c l e W a i t ( a u t o )
  • Page 88 TOSHIBA TMPR3904F Rev. 2.0 (3) DRAM access by the external bus master (Full speed bus mode; HALF*=high) S i n g l e W r i t e C y c l e W a i t ( a u t o )

  • Page 89: Bit Bus Fast Page Mode Write (Early Write)

    TOSHIBA TMPR3904F Rev. 2.0 8.6.9 32-bit bus fast page mode write (Early write) N O R M A L M O D E F A S T P A G E M O D E W a i t W a i t...

  • Page 90: Cbr Refresh

    TOSHIBA TMPR3904F Rev. 2.0 8.6.11 CBR refresh N o r m a l O p e r a t i o n R E F R E S H O p e r a t i o n R A S P r e c h a r g e...

  • Page 91: External Circuit Connections

    TOSHIBA TMPR3904F Rev. 2.0 External Circuit Connections (1) 16-bit width DRAM connection Channel 0 CAS[3:0]* CAS3* CAS2* CAS1* CAS0* RAS0[3]* UCAS* LCAS* UCAS* LCAS* A[13:2] Bank 3 x16bit x16bit RAS0[2]* Bank 2 x16bit x16bit RAS0[1]* Bank 1 x16bit x16bit RAS0[0]*...
  • Page 92 TOSHIBA TMPR3904F Rev. 2.0 (2) 32-bit width DRAM connection Channel 0 CAS[3:0]* CAS3* CAS2* CAS1* CAS0* RAS0[3]* CAS4* CAS3* CAS2* CAS1* A[13:2] Bank 3 x32bit RAS0[2]* Bank 2 x32bit RAS0[1]* Bank 1 x32bit RAS0[0]* Bank 0 x32bit TMPR3904 D31:24 D23:16...

  • Page 93: Features

    TOSHIBA TMPR3904F Rev. 2.0 ROM CONTROLLER (ROMC) Features The ROM Controller generates signals and timings that are to be necessary to control the ROM and the SRAM. (1) Supports the two-channel ROM control Mask ROM, EPROM, FLASH, and SRAM support Supports read operations only for the Mask ROM/EPROM.

  • Page 94: Block Diagrams

    TOSHIBA TMPR3904F Rev. 2.0 Block Diagrams Figure 9-1 shows the ROMC connection inside the TX3904 and Figure 9-2 shows the internal blocks. TX3904 G-BUS I/F SIGNAL CE1[1:0]* CE0[1:0]* EBIF I/F ROMC SIGNAL OE1*,OE0* SWE* BOOT16 EBIF RESET* A[6:1] GBUS ADDRESS SIGNAL FROM EBIF OUTPUT SWITCH SIGNAL FROM EBIF Fig.

  • Page 95: Registers

    TOSHIBA TMPR3904F Rev. 2.0 Registers Table 9-1 ROM Controller Registers Address Register Symbol Register Name 0xFFFF_9000 RCCR0 Channel Control Register 0 0xFFFF_9004 RBMR0 Base Address Mask Register 0 0xFFFF_9100 RCCR1 Channel Control Register 1 0xFFFF_9104 RBMR1 Base Address Mask Register 1...

  • Page 96: Channel Control Register 0

    TOSHIBA TMPR3904F Rev. 2.0 9.3.1 Channel control register 0 RBA0 : Type : Initial 0x1fc Value RPS0 RPWT0 RWT0 RCS0 RIM0 RPM0 6BUS0 : Type : Initial Value Mnemonic Name of Field Description 31:20 RBA0 ROM channel 0 ROM Control Base Address on Channel 0...
  • Page 97 TOSHIBA TMPR3904F Rev. 2.0 Mnemonic Name of Field Description RCS0 ROM Channel 0 ROM Control Channel Size on Channel 0 memory size Designates the memory size to be assigned to Channel 0. 000: 1 Mbytes 100: 16 Mbytes 001: 2 Mbytes...

  • Page 98: Channel Control Register 1

    TOSHIBA TMPR3904F Rev. 2.0 9.3.2 Channel control register 1 RBA1 : Type : Initial 0x000 Value RPS1 RPWT1 RWT1 RCS1 16BUS1 RIM1 RPM1 : Type : Initial Value Mnemonic Name of Field Description 31:20 RBA1 ROM channel 1 ROM Control Base Address on Channel 1...
  • Page 99 TOSHIBA TMPR3904F Rev. 2.0 Mnemonic Name of Field Description RCS1 ROM Channel 1 ROM Control Channel Size on Channel 1 memory size Designates the memory size to be assigned to Channel 1. 000: 1 Mbytes 100: 16 Mbytes 001: 2 Mbytes...

  • Page 100: Base Address Mask Register 0

    TOSHIBA TMPR3904F Rev. 2.0 9.3.3 Base address mask register 0 RBAM0 : Type 0x000 : Initial Value : Type : Initial Value Mnemonic Name of Field Description ROM Control Base Address Mask on Channel 0 31:20 RBAM0 ROM Channel 0...

  • Page 101: Base Address Mask Register 1

    TOSHIBA TMPR3904F Rev. 2.0 9.3.4 Base address mask register 1 RBAM1 : Type 0x000 : Initial Value : Type : Initial Value Mnemonic Name of Field Description 31:20 RBAM1 ROM Channel 1 ROM Control Base Address Mask on Channel 1...

  • Page 102: Operations

    TOSHIBA TMPR3904F Rev. 2.0 Operations 9.4.1 Channel select The channel select for memory access is conducted by the address that is given onto the GBUS of the internal system bus. Of the addresses, the high-order 12 bits are compared if they are within the range from the base address that is set up in the channel control register to the size that is set up in the size register, and if they are in the range, the channel is selected.
  • Page 103 TOSHIBA TMPR3904F Rev. 2.0 B a n k 1 A c c e s s A c c e s s A d d r e s s A d d r e s s B a n k 1...

  • Page 104: Operation Modes

    TOSHIBA TMPR3904F Rev. 2.0 Memory size 4MB Bank 1 0x1FE0_0000 Bank 0 (Boot ROM) Base address 0x1FC0_0000 =Reset vector When two 2-Mbyte ROMs are used like above, a boot ROM (containing initialization program) has to be connected to bank 0 and another one to bank 1. The boot ROM can be accessed properly in default state immediately after reset.

  • Page 105: Bit Static Bus Sizing

    TOSHIBA TMPR3904F Rev. 2.0 9.4.3 32/16-bit Static Bus Sizing The bus width 32/16 bits of the ROM that is connected to the ROM Channel 0 is designated by an external input pin (BOOT16). The value of this input pin will be taken in to the 16BUS0 of the channel control register 0 at the time of reset.

  • Page 106: Timing Diagrams

    TOSHIBA TMPR3904F Rev. 2.0 Timing Diagrams 9.5.1 32-bit bus single read operation (ROM/SRAM) (1) Memory access by internal bus master S i n g l e R e a d C y c l e ( 4 W a i t )
  • Page 107 TOSHIBA TMPR3904F Rev. 2.0 (2) Memory access by external bus master (Half speed bus mode; HALF*=low) S i n g l e R e a d C y c l e ( 4 W a i t ) S 0 W...
  • Page 108 TOSHIBA TMPR3904F Rev. 2.0 (3) Memory access by external bus master (Full speed bus mode; HALF*=high) S i n g l e R e a d C y c l e ( 4 W a i t ) S 0 W...

  • Page 109: Bit Bus Single Read (32-Bit Word) Operation (Rom/Sram)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.2 16-bit bus single read (32-bit word) operation (ROM/SRAM) (1) ROM and SRAM other than page mode MROM 1 s t R e a d C y c l e ( 4 W a i t )

  • Page 110: Bit Bus Single Read (Half Word) Operation (Rom/Sram)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.3 16-bit bus single read (half word) operation (ROM/SRAM) S i n g l e R e a d C y c l e ( 4 W a i t ) S Y S C L K...
  • Page 111 TOSHIBA TMPR3904F Rev. 2.0 (2) Memory access by external bus master (Half speed bus mode; HALF*=low) S i n g l e R e a d C y c l e ( 4 W a i t ) S 0 W...

  • Page 112: Bit Bus Single Write (Word) Operation (Sram/Flush)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.5 16-bit bus single write (word) operation (SRAM/Flush) 1 s t W r i t e C y c l e ( 3 W a i t ) 2 n d R e a d C y c l e ( 3 W a i t )

  • Page 113: Bit Bus Normal Mode Burst Read Operation (Rom/Sram)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.7 32-bit bus normal mode burst read operation (ROM/SRAM) 1st Word Read Cycle (4 Wait) 2nd Word Read Cycle (4 Wait) Last-1 Word Read Cycle LastWord Read Cycle SBW SBW SB4 SB0 SB3 SB4 GCLK(50MHz) A[31:2]...

  • Page 114: Bit Bus Page Mode Burst Read Operation (Page Mode Mrom)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.8 32-bit bus page mode burst read operation (Page mode MROM) N o r m a l R E A D P a g e R E A D S P 0 S P W S P 3...

  • Page 115: Bit Bus Word Normal Mode Burst Read Operation (Rom/Sram)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.9 16-bit bus word normal mode burst read operation (ROM/SRAM) 1st Word 2ndWord (Last - 1) Word Last Word 1st Half-Word(4 Wait) 2nd Half-Word (4 W ait) 1st Half-Word 2nd Half-Word 1st Half-Word 2nd Half-Word SB4 SB0...

  • Page 116: Bit Bus Page Mode Burst Read (Word) Operation (Page Mode Mrom)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.10 16-bit bus page mode burst read (word) operation (Page mode MROM) 1st Word 2nd Word 3rd Word 4th Word 1st Half-Word (2-W ait) 2nd Half-Word 1st Half-Word 2nd Half-Word 1st Half-Word (2-W ait) 2nd Half-Word...

  • Page 117: Bit Bus Normal Mode Burst Write (Sram)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.11 32-bit bus normal mode burst write (SRAM) 1 s t W o r d W r i t e C y c l e ( 3 W a i t ) 2 n d W o r d W r i t e C y c l e ( 3 W a i t )

  • Page 118: Bit Bus Normal Mode Burst Write (Word) (Sram; We Control Write)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.12 16-bit bus normal mode burst write (word) (SRAM; WE control write) 2 n d H a l f - W o r d W r i t e C y c l e ( 3 W a i t )

  • Page 119: Bit Bus Normal Mode Burst Write (Half Word) (Sram; We Control)

    TOSHIBA TMPR3904F Rev. 2.0 9.5.13 16-bit bus normal mode burst write (half word) (SRAM; WE control) 1 s t W o r d W r i t e C y c l e ( 3 W a i t )

  • Page 120: Examples Of Mrom/Eprom Usage

    TOSHIBA TMPR3904F Rev. 2.0 Examples of MROM/EPROM Usage The following figures are the usage examples of MROM/EPROM. C h a n n e l 0 O E 0 * O E * O E * O E * O E *...
  • Page 121 TOSHIBA TMPR3904F Rev. 2.0 C h a n n e l 0 O E 0 * O E * O E * A[n:0] B A N K 1 C E * 1 6 - b i t 1 6 - b i t...

  • Page 122: Examples Of Sram Usage

    TOSHIBA TMPR3904F Rev. 2.0 C h a n n e l 0 O E 0 * O E * A [ 3 1 : 1 ] A [ n : 0 ] B A N K 1 x 1 6...
  • Page 123 TOSHIBA TMPR3904F Rev. 2.0...

  • Page 124: Dma Controller (Dmac)

    TOSHIBA TMPR3904F Rev. 2.0 DMA CONTROLLER (DMAC) The TX3904 has two modules of built-in DMA controllers (DMAC) with two channels. 10.1 Features The following are the features of the DMAC built-in in the TX3904. (1) Independent two-channel DMA (Two modules are connected with a daisy-chain)

  • Page 125: Configuration

    TOSHIBA TMPR3904F Rev. 2.0 10.2 Configuration 10.2.1 TX3904 internal connection The following Figure 10-1 shows the DMAC connection inside the TX3904. D R E Q [1:0] D A C K [ 1 : 0 ] D R E Q [3:2] D A C K [ 3 : 2 ]...

  • Page 126: Dmac Internal Blocks

    TOSHIBA TMPR3904F Rev. 2.0 bus ownership requests, the SREQ has a higher priority than the GREQ. Therefore, the priority between the two DMAC modules depends on the daisy-chain connection when the bus ownership request mode is the same, and it depends on the bus ownership request mode when the kinds of the bus ownership differ.
  • Page 127 TOSHIBA TMPR3904F Rev. 2.0 DMAC0 and DMAC1 are daisy-chain connected. When DMAC0 and DMAC1 are both using the snoop function or are both not using it, the priority is determined by the daisy-chain connection; and DMAC0 has a higher priority than DMAC1.

  • Page 128: Registers

    TOSHIBA TMPR3904F Rev. 2.0 10.3 Registers The following diagram shows fourteen built-in 32-bit registers of the DMAC. Tables 10-1 and 10-2 show the register maps of DMAC0 and DMAC1. Table 10-1 DMAC0 Registers Address Register Name of Register Symbol 0xFFFF-A08C...

  • Page 129: Dma Control Register (Dcr)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.1 DMA control register (DCR) : Type : Initial Value : Type : Initial Value Mnemonic Name of Description Field Reset Reset Conducts software reset of the DMAC. The DMAC shall be initialized when the Rst bit is set to 1. All the values of the DMAC internal registers become the initial values.

  • Page 130: Channel Control Register (Ccrn)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.2 Channel control register (CCRn) Stop NIEn AbIEn CIEn DIEn DOEn Cont R/W R/W R/W R/W R/W : Type : Initial Value PosE SReq RelEn TrSiz R/W R/W R/W R/W R/W R/W R/W : Type : Initial...
  • Page 131 TOSHIBA TMPR3904F Rev. 2.0 CIEn Continue Continuous Mode Interrupt Enable interrupt 1: Grants the continue mode interrupt enable 0: Inhibits the continue mode interrupt DIEn DONE input DONE Interrupt Enable enable Validates the input of DONE* signal. 1: Finishes transfer operation when DONE* has become low.
  • Page 132 TOSHIBA TMPR3904F Rev. 2.0 PosE Rising edge Positive Edge Designates the valid level of the transfer request signal DREQn. This is valid only when the transfer request is an external transfer request (the ExR bit is 1). When it is an internal transfer request (the ExR bit is 0), the value of the PosE shall be ignored.
  • Page 133 TOSHIBA TMPR3904F Rev. 2.0 RelEn Release Request Enable ownership Designates the response to the bus ownership release release request from the TX39 Processor Core. request 1: Bus ownership release request is answered. When the enable TX39 Processor Core issues a bus ownership release...

  • Page 134: Channel Status Register (Csrn)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.3 Channel status register (CSRn) Conf : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description Channel Channel Active active Indicates that the channel is in the wait status. 1: Channel is in the wait status.
  • Page 135 TOSHIBA TMPR3904F Rev. 2.0 Abnormal Abnormal Completion completion Indicates that the channel operation has completed abnormally. If interrupts at the time of an abnormal completion are permitted by the CCR register, the DMAC requests an interrupt when the AbC bit becomes By writing “0”...
  • Page 136 TOSHIBA TMPR3904F Rev. 2.0 BSTART wait BSW(BSTART Wait Cycle) Specifies the BSTART* wait clock count in single address mode I/O to memory transfer. 000: 0 wait cycle 001: 1 wait cycle 111: 7 wait cycles Fig. 10-10 Channel Status Registers (CSRn) (3/3)

  • Page 137: Source Address Register (Sarn)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.4 Source address register (SARn) SAddr : Type : Initial Value SAddr : Type : Initial Value Mnemonic Name of Field Description 31:0 SAddr Source Source Address address Sets up the source address that is to be the data transfer origin with a physical address.

  • Page 138: Destination Address Register (Darn)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.5 Destination address register (DARn) DAddr : Type : Initial Value DAddr : Type : Initial Value Mnemonic Name of Field Description 31:0 DAddr Destination Destination Address address Sets up the destination address that is to be the data transfer destination with a physical address.

  • Page 139: Byte Count Register (Bcr0N)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.6 Byte count register (BCR0n) : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description 23:0 Byte count Byte Count Sets up the number of bytes to be data transferred. The value decreases by the number of data transferred (by the value designated in the TrSiz of the CCRn).

  • Page 140: Next Byte Count Register (Ncr0/1)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.7 Next byte count register (NCR0/1) : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description 23:0 Next byte Next Byte Count count Sets up the number of transfer bytes of the next data transfer in the continue mode.

  • Page 141: Data Holding Register (Dhr)

    TOSHIBA TMPR3904F Rev. 2.0 10.3.8 Data holding register (DHR) : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description 31:0 Transfer data Data on Transfer The data that were transferred in the dual address mode and were read from the source.

  • Page 142: Functions

    TOSHIBA TMPR3904F Rev. 2.0 10.4 Functions This section explains the functions of DMAC0. DMAC1 has the same functions as DMAC0. 10.4.1 Overview The DMAC is a 32-bit DMA controller that can transfer data inside the system using the TX39 Processor Core at a high speed without the TX39 Processor Core.
  • Page 143 TOSHIBA TMPR3904F Rev. 2.0 transfer requests by the level detection of the DREQn signal and a edge mode that generates transfer requests by the edge detection of the DREQn signal. (4) Address modes There are two address modes--a single address mode and a dual address mode.
  • Page 144 TOSHIBA TMPR3904F Rev. 2.0 No bus ownership WAIT Operate Stop=1 HALT No bus Bus ownership ownership Transfer Completion TRANSFER Bus ownership Fig.10-16 Status Shifts between Channel Operations...
  • Page 145 TOSHIBA TMPR3904F Rev. 2.0 (7) Summary of transfer method combinations The following table shows the transfers that can be done by the DMAC by combining the modes. Transfer Request Edge/Level Address Mode Continue Mode Transfer Device Memory → Memory Internal...

  • Page 146: Transfer Requests

    TOSHIBA TMPR3904F Rev. 2.0 10.4.2 Transfer requests In order to conduct a data transfer by the DMAC, it is necessary to generate a transfer request to the DMAC. There are two kinds in the DMAC’s transfer requests--an internal transfer request and an external transfer request.
  • Page 147 TOSHIBA TMPR3904F Rev. 2.0 Since three of DREQ[3:1] is synchronized by the SYSCLK, they are noticed to the DMAC with a delay of one SYSCLK. The DREQ[0] is not synchronized so it is directly informed to the DMAC. S Y S C L K...
  • Page 148 TOSHIBA TMPR3904F Rev. 2.0 Level Mode In the level mode, the internal DREQn signal (dreq) is level-detected at a rising of the internal clock (GCLK). If the active level is detected in the dreq signal when the channel is in the wait status, the DMAC switches to the transfer status to start data transfer.
  • Page 149 TOSHIBA TMPR3904F Rev. 2.0 Edge Mode In the edge mode, the internal DREQn signal (dreq) is edge-detected. If the valid edge of the dreq signal is acknowledged at a rising of the internal clock (GCLK) (if it is presently at the...

  • Page 150: Address Modes

    TOSHIBA TMPR3904F Rev. 2.0 10.4.3 Address modes At the address mode, the DMAC outputs addresses to both the source device and the destination device to conduct transfer operations or it outputs its address to one of the devices to designate whether or not the transfer operation shall be implemented.
  • Page 151 TOSHIBA TMPR3904F Rev. 2.0 D M A C S o u r c e d e v i c e A d d r e s s A d d r e s s b u s D a t a...
  • Page 152 TOSHIBA TMPR3904F Rev. 2.0 Dual address mode The dual address mode is a mode that executes the transfer by the following two bus operations:  A read operation to output the address of the source device and to read the data from the source device to take them in to the register (DHR) inside the DMAC.
  • Page 153 TOSHIBA TMPR3904F Rev. 2.0 Table 10-3 Data Transfer Unit and Device Port Size (Dual Address Mode) TrSiz Bus Operation for I/O Device One time Two times Four times Set up inhibited One time Two times Set up inhibited Set up inhibited...
  • Page 154 TOSHIBA TMPR3904F Rev. 2.0 Single address mode The single address mode enables the transfer between a memory and an I/O device. The DMAC outputs the memory address to the memory and outputs the DACKn signal to the I/O device. The data transfer between the memory and the I/O device is conducted in one bus operation.

  • Page 155: Burst Transfer

    TOSHIBA TMPR3904F Rev. 2.0 10.4.4 Burst transfer In the single address mode, the burst transfer is supported for the fast data transfer. It is available for the data transfer between 32-bit width memory and 32-bit width I/O device. Set 0x (32 bits) to the TrSiz and 11 (8 bits) to the DPS in the single address mode in order to use burst transfer.

  • Page 156: Channel Operation

    TOSHIBA TMPR3904F Rev. 2.0 10.4.6 Channel operation The channels are turned on when the Str bit of the CCRn of each channel is set to 1. When a channel is turned on, a starting check-up is conducted; and if there is no error, the channel shall be in the wait status.
  • Page 157 TOSHIBA TMPR3904F Rev. 2.0 Abnormal completion The following cases are the abnormal completion of the DMAC. Completion by configuration error The configuration error is a mistake in the set-up of the DMA transfer. A configuration error occurs before a data transfer operation is started so that the values of SARn, DARn, and BCRn are the same as the set-up time.
  • Page 158 TOSHIBA TMPR3904F Rev. 2.0 Priority of channels The priority of Channel 0 is always higher of the two channels of the DMAC. Therefore, if Channel 0 and Channel 1 simultaneously generate transfer requests, the transfer operation to the transfer request of Channel 0 is conducted first. If Channel 1 still has the transfer request when the transfer request of Channel 0 is no longer there, the transfer operation of Channel 1 is executed (Internal transfer requests are maintained unless the transfer requests are cleared;...
  • Page 159 TOSHIBA TMPR3904F Rev. 2.0 Interrupts The DMAC can request interrupts of the TX39 Processor Core at the channel operation completion. In interrupt, the are three kinds--a normal interrupt, an abnormal interrupt, and a continue interrupt. Normal interrupt When a channel operation has completed normally, the NC bit of the CSRn is set to 1. At this time, if the normal completion interrupt is permitted in the NIEn bit of the CCRn, an interrupt is requested of the TX39 Processor Core.

  • Page 160: Endian Switch Function

    TOSHIBA TMPR3904F Rev. 2.0 10.4.7 Endian switch function When the data transfer unit and the device port size are different in the dual address mode, the DMAC combines or disassembles the data in the DHR. For example, if the port size of the I/O device that is the source device is 8 bits and the data...

  • Page 161: Operations

    TOSHIBA TMPR3904F Rev. 2.0 10.5 Operations The DMAC’s operation is conducted synchronously with the rising edges of the SYSCLK. 10.5.1 Dual address mode Memory to memory transfer The following Fig. 9-22 shows the timing of one word in the case where the data are transferred from a DRAM to another DRAM.
  • Page 162 TOSHIBA TMPR3904F Rev. 2.0 Memory to I/O device transfer Fig. 9-23 shows the timing of a memory to I/O device transfer when the data transfer unit is set at 32 bits and the device port size at 16 bits: S Y S C L K...
  • Page 163 TOSHIBA TMPR3904F Rev. 2.0 I/O device to memory transfer Fig. 9-24 shows the timing of an I/O device to memory transfer when the data transfer unit is set at 32 bits and the device port size at 32 bits: S Y S C L K...

  • Page 164: Single Address Mode

    TOSHIBA TMPR3904F Rev. 2.0 10.5.2 Single address mode In the single address mode, the acknowledge signal is driven by the TX3904 built-in memory controller so that it is not necessary to input from outside. The R/W* signal indicates the bus operation for the memory.
  • Page 165 TOSHIBA TMPR3904F Rev. 2.0 I/O device to Memory Fig. 9-26 shows the timing of an I/O device to memory transfer when the data transfer unit is set at 32 bits and the device port size at 32 bits (half speed bus mode). This figure illustrates when 2 wait cycles are set to the channel status register BSW field.
  • Page 166 TOSHIBA TMPR3904F Rev. 2.0 Burst mode Fig. 9-27 shows the timing of a memory to I/O device burst transfer operation when the data transfer unit is set at 32 bits and the device port size at 8 bits: S Y S C L K...

  • Page 167: Input Of Done* Signal

    TOSHIBA TMPR3904F Rev. 2.0 10.5.3 Input of DONE* signal When the DIEn bit in the CCRn is set to 1, the DMAC ends the data transfer if the DONE* signal is asserted during a data transfer. The timing to acknowledge the DONE* signal is at the rising of the GCLK recognizing the last internal acknowledge signal in the transfer unit.

  • Page 168: Output Of Done* Signal

    TOSHIBA TMPR3904F Rev. 2.0 10.5.4 Output of DONE* signal When the DOEn bit in the CCRn is set to 1, the DONE* signal is driven at the last data transfer in the single address mode or at the last I/O access of the last data transfer in the dual address mode.
  • Page 169 TOSHIBA TMPR3904F Rev. 2.0...

  • Page 170: Interrupts

    TOSHIBA TMPR3904F Rev. 2.0 INTERRUPTS The TX3904 has one non-maskable interrupt (NMI*) and eight external interrupt (INT[7:0]) pins. In addition to these, there are other interrupts that occur inside the TX3904. This chapter handles these interrupts. 11.1 Features The TX3904 interrupts have the following characteristics:...

  • Page 171: Configuration

    TOSHIBA TMPR3904F Rev. 2.0 11.2 Configuration I N T [ 0 ] E x t e r n a l i n t e r r u p t s i g n a l I R C T X 3 9...

  • Page 172: Functions

    TOSHIBA TMPR3904F Rev. 2.0 11.3 Functions 11.3.1 Interrupt sources The TX3904 has the following interrupt sources. (Maskable) interrupts Table 11-1 shows the interrupt sources of the TX3904. The priority of Numbers 0-15 interrupts is arbitrated by the IRC and the interrupt with the highest priority is informed to the TX39 Processor Core.

  • Page 173: Interrupt Detection

    TOSHIBA TMPR3904F Rev. 2.0 11.3.2 Interrupt detection The active status of an interrupt by the INT[7:0] can be set up in the EIM field of the CConR. There are the high level, low level, rising edge, and falling edge in the active status. The TX3904 interrupt detection circuit notifies of an interrupt request to the TX39 Processor Core or the IRC when it has acknowledged the set up status.

  • Page 174: Registers

    TOSHIBA TMPR3904F Rev. 2.0 11.4 Registers This section describes the registers of the IRC that arbitrates interrupts. For the set-up of the interrupt detection circuit, please refer to the explanations of the chip configuration register (CConR) in Chapter 5. 11.4.1 Register map...

  • Page 175: Interrupt Status Register (Isr)

    TOSHIBA TMPR3904F Rev. 2.0 11.4.2 Interrupt status register (ISR) Indicates the status of each interrupt source. There is an interrupt request when it is 0, and no interrupt request when it is 1. Please note that a suffix number of interrupt status indicates an interrupt number.

  • Page 176: Interrupt Level Registers (Ilr3-Ilr0)

    TOSHIBA TMPR3904F Rev. 2.0 11.4.3 Interrupt level registers (ILR3-ILR0) The interrupt level registers set up the level of the interrupt for each source. The total number of interrupt level registers is four. The following diagram shows the example of the level register 0 (ILR0).

  • Page 177: Interrupt Mask Register (Imr)

    TOSHIBA TMPR3904F Rev. 2.0 11.4.4 Interrupt mask register (IMR) Sets up the interrupt level to be masked. : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description Interrupt mask level Interrupt Mask Level Sets up the interrupt mask level. The interrupt sources of the levels that are equal to or less than the set-up values shall be masked.

  • Page 178: Serial Ports (Sio)

    TOSHIBA TMPR3904F Rev. 2.0 SERIAL PORTS (SIO) 12.1 Features Non-synchronous serial interface (all-dual RS-232C protocol) controllers. (1) Baud rate generator (2) Modem flow control (CTS/RTS) (3) FIFO (8 bits x eight steps) (4) Multi-controller system support 12.2 Block Diagrams Fig. 9-1 shows the SIO connection inside the TX3904 and Fig. 9-2 shows internal blocks of the SIO.
  • Page 179 TOSHIBA TMPR3904F Rev. 2.0 I n t e r n a l S y s t e m C l o c k S I O C L K B a u d r a t e G e n e r a t o r...

  • Page 180: Registers

    TOSHIBA TMPR3904F Rev. 2.0 12.3 Registers Table 12-1 Registers Register Name Address Register Symbol Line Control Register 0 0xFFFF-F300 SLCR0 Line Status Register 0 0xFFFF-F304 SLSR0 DMA/Interrupt Control Register 0 0xFFFF-F308 SDICR0 DMA/Interrupt Status Register 0 0xFFFF-F30C SDISR0 FIFO Control Register 0...

  • Page 181: Line Control Register (Slcrn)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.1 Line control register (SLCRn) The line control register designates the format of the non-synchronous sending/receiving data. RWUB TWUB UODE UEPS UPEN USBL UMODE : Type :Initial Value : Type : Initial Value Mnemonic Name of...
  • Page 182 TOSHIBA TMPR3904F Rev. 2.0 Mnemonic Name of Description Field Hand Shake Enable Hand shake Hand shake function control using the CTS. enable 0: Disable (Sending can always be done.) 1: Enable SIO Clock Select 22:21 Clock select Selects the serial transfer clock. The serial transfer clock is a clock with the frequency 16 times of the baud rate (bps).

  • Page 183: Line Status Register (Slsrn)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.2 Line status register (SLSRn) The status information about the serial data sending/receiving is given to the line status register. UFER UPER UOER : Type : Initial Value : Type : Initial Value Mnemonic Name of...

  • Page 184: Dma/Interrupt Control Register (Sdicrn)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.3 DMA/Interrupt control register (SDICRn) Designates to conduct the host interface either by the DMA or by the interrupt. SDMAE ERIE TDIE RDIE : Type : Initial Value : Type : Initial Value Mnemonic Name of Field...
  • Page 185 TOSHIBA TMPR3904F Rev. 2.0 Receive Receive DMA/Interrupt Enable RDIE data DMA When in interrupt mode (SDMAE = 0) /Interrupt Valid data read request interrupt enable for enable receive FIFO. Asserts the SINTREQ* signal when there is valid data in the receive FIFO.

  • Page 186: Dma/Interrupt Status Register (Sdisrn)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.4 DMA/Interrupt status register (SDISRn) Indicates the status information of the DMA/interrupt. SDMA TDIS RDIS : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description SDMA DMA request DMA Request Indicates that the DMA request is being asserted.
  • Page 187 TOSHIBA TMPR3904F Rev. 2.0 Reception Receive DMA/Interrupt Status RDIS data full When in the Interrupt mode (SDMAE=0) Set to “1” when there is valid data in the receive FIFO. This bit is cleared when a “0” is written to it. Also, when the RDIE bit of the DMA/Interrupt control register is set to “1,”...

  • Page 188: Fifo Control Register (Sfcrn)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.5 FIFO control register (SFCRn) Sets up the control of the transfer/receive FIFO buffers. TFRST RFRST FRSTE : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description Receive FIFO DMA Request Trigger Level...

  • Page 189: Baudrate Control Register (Sbgrn)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.6 Baudrate control register (SBGRn) Conducts the selection of clocks and the set-up of divide values to be given to the baudrate generator. BCLK : Type 0xFF : Initial Value : Type : Initial Value Mnemonic...

  • Page 190: Transmit Fifo Buffer (Tfifon)

    TOSHIBA TMPR3904F Rev. 2.0 12.3.7 Transmit FIFO buffer (TFIFOn) Writes transmission data. : Type : Initial Value : Type : Initial Value Mnemonic Field name Explanation Transmission 31:24 Transmit Data data Writes the transmission data. Fig. 12-12 Transmit FIFO buffer 12.3.8 Receive FIFO buffer (SFIFOn)

  • Page 191: Operations

    TOSHIBA TMPR3904F Rev. 2.0 12.4 Operations 12.4.1 Overview The TX3904 has two channels of SIO’s. The SIO converts serial data from outside that are to be input to the SIN to parallel data by the shift register. The converted parallel data shall be stored in the receive FIFO buffer.
  • Page 192 TOSHIBA TMPR3904F Rev. 2.0 The following diagrams show the data frame configuration. 8 - b i t D a t a T r a n s f e r d i r e c t i o n S t a r t...

  • Page 193: Serial Clock Generator

    TOSHIBA TMPR3904F Rev. 2.0 12.4.3 Serial clock generator Select the baud rate generator circuit output or internal system clock IMCLK. Then, make it the SIOCLK (transmit/receive clock which determines the serial I/O transfer speed). I M C L K ( f c / 2 )
  • Page 194 TOSHIBA TMPR3904F Rev. 2.0 B a u d r a t e G e n e r a t o r I n p u t C l ock fc[MH z] BRG Divider fc/4 fc/16 fc/64 fc/256 50.00 156.25 39.06 9.77...

  • Page 195: Receiver Controller

    TOSHIBA TMPR3904F Rev. 2.0 12.4.5 Receiver Controller For the receive control, the start bit is detected by the majority logic to start a data receiving operation. Data receiving is conducted also by the majority logic. The start bit and the receiving of the data 1 bit are sampled at SIOCLK 16 clocks.

  • Page 196: Hand Shake Function

    TOSHIBA TMPR3904F Rev. 2.0 In the reading-out by the DMA transfer, when receiving data of 4 bytes or 8 bytes are sent to the receive FIFO buffer (when the write pointer (0-7) becomes 4 and 0), a DMA request is generated and the receiving data are written in to the memory.

  • Page 197: Parity Control

    TOSHIBA TMPR3904F Rev. 2.0 12.4.12 Parity control In a transfer operation, the parity control circuit automatically generates a parity by the data that were written into the transfer shift register; and the parity is stored to the bit7 (the highest-order) of the transfer shift register when the data length is 7 bits and to the TWUB of the line control register when the data length is 8 bits to transfer it.
  • Page 198 TOSHIBA TMPR3904F Rev. 2.0 (2) The slave controller prepares the address (ID) frame for receiving from the master controller by setting the RWUB of the line control register to 1. (3) The master controller sends the address (ID) (8-bit or 7-bit) of the slave controller by setting the WUB of the sending frame to 1 (the line control register TWUB = 1).

  • Page 199: Timing Explanations

    TOSHIBA TMPR3904F Rev. 2.0 12.5 Timing Explanations 12.5.1 Operation at the time of receiving (7 and 8 bit data length) 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 S I O C L K...

  • Page 200: Operation At The Time Of Receiving (8 And 9 Bit Length Multi-Controller System

    TOSHIBA TMPR3904F Rev. 2.0 12.5.3 Operation at the time of receiving (8 and 9 bit length multi-controller system; RWUB = 1 when standing by for ID receiving) 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1...
  • Page 201 TOSHIBA TMPR3904F Rev. 2.0 12.5.5 Operation at the time of receiving (8 and 9 bit length multi-controller system; RWUB = 1 when receiving data and discarding) 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1...

  • Page 202: Transmit Halt Timing By Cts

    TOSHIBA TMPR3904F Rev. 2.0 12.5.7 Transmit halt timing by CTS* S I O C L K C T S * S h i f t - O u t T i m i n g S O U T S t o p B i t...
  • Page 203 TOSHIBA TMPR3904F Rev. 2.0...

  • Page 204: Timers/Counters

    TOSHIBA TMPR3904F Rev. 2.0 TIMERS/COUNTERS 13.1 Features The timers/counters that are built-in in the TX3904 have the following three modes that use the 24-bit up counter: (1) Interval Timer Mode Generates regular interrupts Can select the external input clock. Can count external events by using the external input clock.
  • Page 205 TOSHIBA TMPR3904F Rev. 2.0 IM-BUS T I M E R C H A N N E L S 2 , 1 , A N D 0 R e g i s t e r T i m e r R e a d...

  • Page 206: Registers

    TOSHIBA TMPR3904F Rev. 2.0 13.3 Registers Table 13-1 Timer Registers (Timer 2) Address Register Register Name Symbol 0xFFFF_F200 TCR2 Timer Control Register 2 0xFFFF_F204 TISR2 Timer Interrupt Status Register 2 0xFFFF_F208 CPRA2 Compare Register A2 0xFFFF_F20C CPRB2 Compare Register B2...
  • Page 207 TOSHIBA TMPR3904F Rev. 2.0 Table 13-3 Timer Registers (Timer 0) Address Register Register Name Symbol 0xFFFF_F000 TCR0 Timer Control Register 0 0xFFFF_F004 TISR0 Timer Interrupt Status Register 0 0xFFFF_F008 CPRA0 Compare Register A0 0xFFFF_F00C CPRB0 Compare Register B0 0xFFFF_F010 ITMR0...
  • Page 208 TOSHIBA TMPR3904F Rev. 2.0 13.3.1 Timer control registers 2, 1, and 0 (TCR2, 1, 0) : Type : Initial Value CCDE ECES TMODE R/W R/W R/W R/W : Type : Initial Value Mnemonic Name of Field Description Timer Count Enable Timer counter Controls the counter operation.
  • Page 209 TOSHIBA TMPR3904F Rev. 2.0 Mnemonic Name of Field Description Counter Clock Select Timer clock Selects the counter clock. select 0: Internal system clock 1: External input clock Timer Mode TMODE Timer mode Designates the operation mode of the timer. 11: Set-up disabled...
  • Page 210 TOSHIBA TMPR3904F Rev. 2.0 13.3.2 Interval timer mode registers 0, 1, and 2 (ITMR2, 1, 0) : Type : Initial Value TIIE TZCE : Type : Initial Value Mnemonic Name of Field Description Timer Interval Interrupt Enable TIIE Interval timer Sets up interrupt enable/disable in interval timer mode.
  • Page 211 TOSHIBA TMPR3904F Rev. 2.0 13.3.3 Divider registers 2, 1, and 0 (CCDR2, 1, 0) : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description Counter Clock Divide Counter clock Designates the divider when the internal system clock divider is used for the counter input clock source.
  • Page 212 TOSHIBA TMPR3904F Rev. 2.0 13.3.4 Pulse generator mode registers 2 and 1 (PGMR2, 1) : Type : Initial Value TPIBE TPIAE : Type : Initial Value Mnemonic Name of Field Description Timer Pulse Generator Interrupt by CPRB Enable TPIBE CPRB...

  • Page 213: Watchdog Timer Mode Register 2 (Wtmr2)

    TOSHIBA TMPR3904F Rev. 2.0 13.3.5 Watchdog timer mode register 2 (WTMR2) : Type : Initial Value TWIE WDIS : Type : Initial Value Mnemonic Name of Field Description Timer Watchdog Interrupt Enable TWIE Watchdog Sets up interrupt enable/disable in the watchdog timer timer interrupt mode.
  • Page 214 TOSHIBA TMPR3904F Rev. 2.0 13.3.6 Timer interrupt status registers 2, 1 and 0 (TISR2, 1, 0) : Type : Initial Value TWIS TPIBS TPIAS TIIS : Type : Initial Value Mnemonic Name of Field Description Timer Watchdog Interrupt Status TWIS...
  • Page 215 TOSHIBA TMPR3904F Rev. 2.0 Mnemonic Name of Field Description Timer Pulse Generator Interrupt by CPRA Status TPIAS Pulse generator When the TPIAS is enable and when the counter value CPRA matches the compare register CPRA, the TPIAS is set interrupt status to assert the TMINTREQ*.
  • Page 216 TOSHIBA TMPR3904F Rev. 2.0 13.3.7 Compare registers A 2, 1 and 0 (CPRA2, 1, 0) TCVB : Type : Initial Value TCVB : Type 0xFFFFFF : Initial Value Mnemonic Name of Field Description Timer Compare Value 23:0 TCVA Timer compare Sets up the compare value of the timer.
  • Page 217 TOSHIBA TMPR3904F Rev. 2.0 13.3.9 Timer read registers 2, 1 and 0 (TRR2, 1, 0) TCNT : Type : Initial Value TCNT : Type 0x000000 : Initial Value Mnemonic Name of Field Description Timer Count 23:0 TCNT Timer count The 24-bit counter value is copied to this register.

  • Page 218: Operations

    TOSHIBA TMPR3904F Rev. 2.0 13.4 Operations This section describes the case of Timer 2 because the operations are the same for Timers 2, 1 and 0. If there are differences on different channels, they shall be explained individually. 13.4.1 Interval timer mode It is set up to the interval timer mode by the timer mode (TMODE)=00 of the timer control register (TCRn;...
  • Page 219 TOSHIBA TMPR3904F Rev. 2.0 C o u n t V a l u e C P R A R e g . C o m p a r e V a l u e 0 x 0 0 0 0 0 0...
  • Page 220 TOSHIBA TMPR3904F Rev. 2.0 C o u n t V a l u e C P R A C o m p a r e V a l u e 0 x 0 0 0 0 0 0 T i m e...

  • Page 221: Pulse Generator Mode

    TOSHIBA TMPR3904F Rev. 2.0 13.4.2 Pulse generator mode When the TMODE of the TCRn (n=2,1) is 1, it is the pulse generator mode. In the pulse generator mode, quadrangular waves of at-will frequency and duty can be output using two compare registers--CPRA and CPRB.
  • Page 222 TOSHIBA TMPR3904F Rev. 2.0 C o u n t V a l u e C P R B C o m p a r e V a l u e C P R A C o m p a r e V a l u e...

  • Page 223: Watchdog Timer Mode

    TOSHIBA TMPR3904F Rev. 2.0 13.4.3 Watchdog timer mode In the TX3904, only the watchdog timer interrupt request signal (WDTINTREQ*) of the timer/counter Channel 2 can be connected to the internal NMI* or the reset circuit. The connection target of the WDTINTREQ* signal is selected in the WR bit of the chip configuration register CConR.

  • Page 224: Timing Explanations

    TOSHIBA TMPR3904F Rev. 2.0 13.5 Timing Explanations 13.5.1 Interval timer mode interrupt timing T I M E R I N P U T C L O C K T C R 2 , 1 , 0 < T C E >...

  • Page 225: Pulse Generator Mode F/F Output Timing

    TOSHIBA TMPR3904F Rev. 2.0 13.5.2 Pulse generator mode F/F output timing T I M E R I N P U T C L O C K T C R 2 , 1 < T C E > C O U N T V A L U E...

  • Page 226: Io Ports (Pio)

    TOSHIBA TMPR3904F Rev. 2.0 IO PORTS (PIO) The TX3904 has one channel exclusive PIO and two channels of shared PIO’s. One channel comprises a 8-bit port. The exclusive PIO (PIO0) uses the PIO0[7:0] signal. In the shared PIO’s (PIO2 and PIO1), the PIO2[7:0] and PIO1[7:0] signals share pins with other signals.

  • Page 227: Registers

    TOSHIBA TMPR3904F Rev. 2.0 14.3 Registers Figure 14-3 shows the register map of the PIO’s. Table 14-3 PIO Register Map Address Module Register Name 0xFFFF_F704 PIO2 Data Register 2 (PDR2) 0xFFFF_F700 PIO2 Direction Register 2 (POR2) 0xFFFF_F604 PIO1 Data Register 1 (PDR1)
  • Page 228 TOSHIBA TMPR3904F Rev. 2.0 14.3.1 PIO data registers (PDR2, 1, 0) R/W R/W R/W R/W R/W R/W R/W R/W : Type : Initial Value : Type : Initial Value Mnemonic Name of Field Description Port data 7 Port Data [7] Maintains the input/output data of the PIOn[7] signal.
  • Page 229 TOSHIBA TMPR3904F Rev. 2.0 14.3.2 PIO direction registers (POR2, 1, 0) : Type R/W R/W R/W R/W R/W R/W R/W R/W : Initial Value : Type : Initial Value Mnemonic Name of Field Description Port output mode Port Output Mode [7] Sets up the direction of the PIOn[7] signal.

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