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CLG OSC1 Control Register
Register name
Bit
CLGOSC1
15
14
13
12
11
10–8
7–6
5–4
3–2
1–0
Bit 15
Reserved
Bit 14
OSDRB
This bit enables the OSC1 oscillator circuit restart function by the oscillation stop
detector when OSC1 oscillation stop is detected.
1 (R/WP):
(Restart the OSC1 oscillator circuit when oscillation stop is detected.)
0 (R/WP):
Bit 13
OSDEN
This bit controls the oscillation stop detector in the OSC1 oscillator circuit.
1 (R/WP):
0 (R/WP):
Note:
Do not write 1 to the CLGOSC1.OSDEN bit before stabilized OSC1CLK is supplied. Further-
more, the CLGOSC1.OSDEN bit should be set to 0 when the CLGOSC.OSC1EN bit is set to 0.
Bit 12
OSC1BUP
This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit.
1 (R/WP):
0 (R/WP):
Bit 11
OSC1SELCR
This bit selects an oscillator type of the OSC1 oscillator circuit.
1 (R/WP):
0 (R/WP):
Bits 10–8
CGI1[2:0]
These bits set the internal gate capacitance in the OSC1 oscillator circuit.
For more information, refer to "OSC1 oscillator circuit characteristics, Internal gate
capacitance C
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0
OSDRB
1
OSDEN
0
OSC1BUP
1
OSC1SELCR
0
CGI1[2:0]
0x0
INV1B[1:0]
0x2
INV1N[1:0]
0x1
–
0x0
OSC1WT[1:0]
0x2
Enable
Disable
OSC1 oscillation stop detector on
OSC1 oscillation stop detector off
Enable (Activate booster operation at startup.)
Disable
Internal oscillator
Crystal oscillator
Table 2.6.5 OSC1 Internal Gate Capacitance Setting
CLGOSC1.CGI1[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
" in the "Electrical Characteristics" chapter.
GI1
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/WP
H0
R/WP
H0
R/WP
H0
R/WP
H0
R/WP
H0
R/WP
H0
R/WP
–
R
H0
R/WP
Capacitance
Max.
↑
↓
Min.
Remarks
–
2-25
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