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SECTION 6. CIRCUIT DESCRIPTION
6-1 BLOCK AND SCHEMATIC DIA-
GRAMS
A block diagram of your DG-5 is shown in
Figure 8 and a schematic diagram in page 15.
The whole circuit consists chiefly of a signal
amplifier, an analog mixer, a digital counter,
and a power supply.
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2 PRINCIPLES OF OPERATION
The TS-520S operating frequency is made
up as: HET — (VFO + CAR).
In the DG-5 where two counter circuits are
connected in series, the heterodyne signal is
fed to the lower counter. This lower counter
subtracts 10MHz from the heterodyne frequency
in a digital way (HET-10MHz). The subtracted
frequency presets the upper counter. The other
signal fed to the upper counter is composed
in the manner that the carrier frequency is mixed
with the 10MHz reference frequency and the
resultant is further mixed with the VFO fre-
quency [(10MHz—CAR) — VFO] . This signal
is added to the one preset by the lower counter,
that is:
[(10MHz—CAR) — VFO] + (HET — 10MHz)
= HET — (VFO + CAR).
As explained above, you will find that the
DG-5 should display the conect TS-520S operat-
ing frequency. The reason of using such a
complicated construction is that if the DG-5
is the same as the TS-520S in the construction,
this can produce a signal of the same frequency
as the receive frequency. The signal interferes as
spurious with the operation of the TS-520S.
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