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It measures the timing that data processed in DIC1 at DVD playback enters DIC6
SBGN
SDCK
SREQ
SENB
SERR
SDATA
It shows the timing of control signal, address and data bus when micom accesses DIC1 and DIC6.
So to speak, timing at writing a value in the internal register of DIC1 and DIC6.
/DPCS
/WAIT
/WR
/RD
HADRS all
HAD
all
It shows a waveform that DIC1 requests a management to micom by interrupt generation.
Micom recognizes the interrupt and writes a value in register of DIC1 to respond (instruction) for interrupt.
Micom accesses DIC1 five times in Figure. Micom recognizes the operation of chip and makes a necessary
instruction after receiving the interrupt generated in DIC1 and DIC6 and accessing the corresponding chip.
The instruction is executed by acessing the corresponding chip and writing a value(digital) into register.
Micom accesses DIC1 via DIC6.
The block diagram shows that the same type as signal line connecting DIC6 and micom is composed between
DIC1 and DIC6. That is, DIC1 is interfaced with micom through DIC6.
/DPCS
/WAIT
/WR
/RD
HADRS all
HAD
all
¥ CH1 : DPCS (DIC6-76, TC90A19/TC6804F chip select)
¥ CH2 : DPRINT (DIC1-23, DIC6-80, TC90A19F/TC6804F interface)
¥ CH3 : WR (DIC6-78, TC90A19F/TC6804F register write)
¥ CH4 : RD (DIC6-77, TC90A19F/TC6804F register read)
¥ CH5 : HADRS (DIC6-74, 75, Micom address bus)
¥ CH6 : HAD (DIC6-65 to 72, Micom data bus)
2-24
Fig. 2-44
Fig. 2-45
¥ CH1 : SBGN (DICI-92, SECTOR BEGIN)
¥ CH2 : SDCK (DICI-94, CLOCK)
¥ CH3 : SREQ (DICI-96, DATA REQUEST)
¥ CH4 : SERR (DICI-91, DATA ERROR)
¥ CH5 : SDATA (DICI-81~84, 87~90, DATA)
¥ CH1 : DPCS (DIC6-76, TC90A19/TC6804F chip
select)
¥ CH3 : WR (DIC6-78, TC90A19F/TC6804F
register write)
¥ CH4 : RD (DIC6-77, TC90A19F/TC6804F
register read)
¥ CH5 : HADRS (DIC6-74, 75, Micom address
bus)
¥ CH6 : HAD (DIC6-65 to 72, Micom data bus)
Fig. 2-46
Samsung Electronics
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