Register Description - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller

REGISTER DESCRIPTION

Each Timer contains the registers shown in Table 156. More detailed descriptions follow.
Table 156: TIMER0 and TIMER1 Register Map
TIMER0
Generic
Address &
Name
Name
0xE0004000 0xE0008000
IR
T0IR
0xE0004004 0xE0008004
TCR
T0TCR
0xE0004008 0xE0008008
TC
T0TC
0xE000400C 0xE000800C
PR
T0PR
0xE0004010 0xE0008010
PC
T0PC
0xE0004014 0xE0008014
MCR
T0MCR
0xE0004018 0xE0008018
MR0
T0MR0
0xE000401C 0xE000801C
MR1
T0MR1
0xE0004020 0xE0008020
MR2
T0MR2
0xE0004024 0xE0008024
MR3
T0MR3
0xE0004028 0xE0008028
CCR
T0CCR
0xE000402C 0xE000802C
CR0
T0CR0
0xE0004030 0xE0008030
CR1
T0CR1
0xE0004034 0xE0008034
CR2
T0CR2
0xE0004038 0xE0008038
CR3
T0CR3
0xE000403C 0xE000803C
EMR
T0EMR
*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.
Timer0 and Timer1
TIMER1
Address &
Name
Interrupt Register. The IR can be written to clear interrupts. The IR
can be read to identify which of eight possible interrupt sources are
T1IR
pending.
Timer Control Register. The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset
T1TCR
through the TCR.
Timer Counter. The 32-bit TC is incremented every PR+1 cycles of
T1TC pclk. The TC is controlled through the TCR.
Prescale Register. The TC is incremented every PR+1 cycles of
T1PR
pclk.
Prescale Counter. The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC
T1PC
is incremented.
Match Control Register. The MCR is used to control if an interrupt
T1MCR
is generated and if the TC is reset when a Match occurs.
Match Register 0. MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt
T1MR0
every time MR0 matches the TC.
Match Register 1. See MR0 description.
T1MR1
Match Register 2. See MR0 description.
T1MR2
Match Register 3. See MR0 description.
T1MR3
Capture Control Register. The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether
T1CCR
or not an interrupt is generated when a capture takes place.
Capture Register 0. CR0 is loaded with the value of TC when there
T1CR0 is an event on the CAP0.0(CAP1.0) input.
Capture Register 1. See CR0 description.
T1CR1
Capture Register 2. See CR0 description.
T1CR2
Capture Register 3. See CR0 description.
T1CR3
External Match Register. The EMR controls the external match
T1EMR
pins MAT0.0-3 (MAT1.0-3).
LPC2119/2129/2292/2294
Description
182
Preliminary User Manual
Reset
Access
Value*
R/W 0
R/W 0
RW 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
RO 0
RO 0
RO 0
RO 0
R/W 0
January 08, 2004