Motorola MC68838 User Manual page 32

The FSl_BEACON bit has no effect unless the MAC chip is in the beacon state (state
T5). Also, when FSl_BEACON is one, only the BCN_Frame, Append_CRC, and
Extra_FS fields of the packet request header have any effect. The FC and address fields
of the frames sent from the FSI are not checked in any way, though a bad CRC will still
generate the BAD_CRC_SENT interrupt.
DELAY_TOKEN—Wait for FSI Data while Holding the Token
0 = When this bit is zero or the M_BIT is zero, then the MAC ensures that exactly
eight idle symbol pairs of preamble are sent between the ending delimiter of the
last frame and the starting delimiter of the following frame or token. If the last
frame transmission was aborted (i.e., no ending delimiter sent), then zero, one, or
two additional idle symbol pairs may be sent, as measured from the last data
symbol pair sent.
1 = The MAC waits up to an additional 32 cycles (a cycle is 80 ns) for the FSI to
transfer a new Tx_Start after a Tx_End transfer (see 8.1 Transmit Data Path
Control) before it releases the token. Specifically, if this bit is one and the M_Bit
of the last Tx_End transfer is one, then the MAC waits as long as it can, while still
guaranteeing that it will transmit no more than 40 idle symbol pairs of preamble
between the ending delimiter of the last frame and the starting delimiter of the
following frame or token.
This function allows for slower delivery of the start of frame data at the MAC-FSI
interface.
IGNORE_SACAM—Ignore Source Address CAM Recognition
If EXT_DA_MATCH is set, then this bit is ignored.
0 = If the MATCH signal is asserted in the second cycle immediately following the last
byte of the SA, then (assuming no special copy modes are set) the SA is stripped
and the frame is flushed.
1 = The MAC ignores the MATCH signal in determining whether the SA matches or
not.
EXT_DA_MATCH—Extended Destination Address Match Control
0 = DA and SA match. Flush the frame currently being received after the second
byte of the SA if the MATCH signal was not asserted, my long address register or
my short address register was not recognized, or the MAC is not in promiscuous
mode. (The LDADDR pin is an output signal.)
1 = Extended DA match allows the user to delay asserting the MATCH or
TR_BR_FWD signals up to and including the last byte of the FCS. The packet
can be flushed at any time by asserting RABORT. SA_CAM match is not
available with this option. (The LDADDR pin becomes an input signal,
TR_BR_FWD . This signal is the power-up condition, extended DA match, and
TR_BR_FWD input.)
This bit is set on power up.
To use the LDADDR pin in normal mode, the user (initialization firmware) must clear this
bit.
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