Fpga Ram; Bus Dir1/Dsp1; Eeprom - Yamaha RX-V673 Service Manual

C1-5. FPGA RAM
SDRAM (IC53)'s reading/writing are checked.
C1-6. BUS DIR1
Communication and bus line connection between microprocessor (IC83) and DIR1 (IC924) are checked.
C1-7. BUS DSP1
Communication and bus line connection between microprocessor (IC83) and DSP1 (IC921) are checked.
C1-8. EEPROM
EEPROM (IC82)'s reading is checked.
C1-9. INVALID ITEM
Not for service.
C1-10. INVALID ITEM
Not for service.
C1-11. INVALID ITEM
Not for service.
C 1 - 5
F P G A _ R A M : O K
OK: No error detected
NG: An error is detected
C 1 - 6
D I R 1 B U S : O K
OK: No error detected
NG: An error is detected
C 1 - 7
D S P 1 B U S : O K
OK: No error detected
NG: An error is detected
C 1 - 8
E E P R O M : O K
OK: No error detected
NG: An error is detected
C 1 - 9
I N V A L I D I T E M
C 1 - 1 0
I N V A L I D I T E M
C 1 - 1 1
I N V A L I D I T E M
RX-V673/HTR-6065/RX-A720
47