Sony PEGA-CC5 Service Manual page 42

PEGA-CC5
• IC Block Diagrams
– MAIN Board –
IC4 TC74VHC126FT (EL)
14 13 12 11 10 9 8
1 2 3 4 5 6 7
IC26 MT48LC4M16A2TG-75-F
ADDRESS BUS
12
12
ROW-
ADDRESS
MUX
REFRESH
12
COUNTER
BANK
2 CONTROL
LOGIC
12
COMMAND
DECODE
MODE
12
REGISTER
COLUMN-
ADDRESS
8 8
COUNTER/
LATCH
ADDRESS BUS
IC15 BA3121F
1 8
OUT1 VCC
VM1 2 7 OUT2
IN1 3 AMP 6 VM2
AMP
GND 4 5 IN2
DATA BUS
BANK
BANK
ROW-
MEMORY
ADDRESS ARRAY
LATCH
& SENSE
DECODER AMP
DATA
16 INPUT 16
I/O GATING,
REGISTER
DQM MASK LOGIC,
READ DATA LATCH,
DATA
WRITE DRIVERS
16 OUTPUT 16
REGISTER
COLUMN
DECODER
DATA BUS
IC27 BH1415F-E2
22 21 20 19 18 17 16 15
SHIFT REGISTER
–
+
L. P. F.
PRE-EMPHASIS
MPX
MUTE
& LIMITER
L. P. F.
1
+
2
–
0
PHASE
DETECTOR
+
VCC
2
1 2 3 4 5 6 7
IC31, 32 TC7MA244FK (EL)
20 VCC
1OE 1 19 2OE
1A1 2 18 1Y1
3 17 2A4
2Y4
1A2 4 16 1Y2
2Y3 5 15 2A3
1A3 6 14 1Y3
2Y2 7 13 2A2
1A4 8 12 1Y4
2Y1 9 11 2A1
GND 10
42 42
IC29 SP3222ECY/TR
EN 1
C1+ 2
V+ 3
C1– 4
C2+ 5
C2– 6
14 13 12 V– 7
T2OUT 8
R2IN 9
R2OUT 10
1 1
50 4
1
19
PROGRAM COUNTER
OSC RF
8 9 10 11
IC33, 34 TC7MA373FK (EL)
OE 1
Q0 2
D Q
D0 3
L
L
D1 4
D Q
Q1 5
Q2 6
D Q
D2 7
L
L
D3 8
D Q
Q3 9
GND 10
20 SHDN
19 VCC
18 GND
17 T1OUT
16 R1IN
15 R1OUT
14 NC
13 T1IN
12 T2IN
11 NC
20 VCC
19 Q7
Q D
18 D7
L
L
17 D6
Q D
16 Q6
15 Q5
Q D
14 D5
L
L
13 D4
Q D
12 Q4
11 LE