Page 1 Hitachi Single-Chip Microcomputer H8S/2199 Series H8S/2199 HD6432199 H8S/2198 HD6432198 H8S/2197 HD6432197 H8S/2196 HD6432196 ™ H8S/2199F-ZTAT HD64F2199 Hardware Manual ADE-602-191 Rev 1.0 2/15/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement....................1.3.2 Pin Functions ....................Section 2 ........................17 Overview........................... 17 2.1.1 Features......................17 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ....... 18 2.1.3 Differences from H8/300 CPU .................
Page 4 2.9.1 Overview ......................59 2.9.2 On-Chip Memory (ROM, RAM)..............59 2.9.3 On-Chip Supporting Module Access Timing ........... 60 Section 3 MCU Operating Modes ................61 Overview........................... 61 3.1.1 Operating Mode Selection ................61 3.1.2 Register Configuration..................61 Register Descriptions ......................62 3.2.1 Mode Control Register (MDCR) ..............
Page 5 Section 5 Exception Handling ..................87 Overview........................... 87 5.1.1 Exception Handling Types and Priority............87 5.1.2 Exception Handling Operation ................. 88 5.1.3 Exception Sources and Vector Table..............88 Reset..........................90 5.2.1 Overview ......................90 5.2.2 Reset Sequence ....................90 5.2.3 Interrupts after Reset..................
Page 6 Section 7 ........................123 Overview........................... 123 7.1.1 Block Diagram....................123 Overview of Flash Memory ....................124 7.2.1 Features......................124 7.2.2 Block Diagram....................125 7.2.3 Flash Memory Operating Modes ..............126 7.2.4 Pin Configuration ..................... 130 7.2.5 Register Configuration..................130 Flash Memory Register Descriptions................131 7.3.1 Flash Memory Control Register 1 (FLMCR1) ..........
Page 7 Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions ..........................169 Section 8 ........................171 Overview........................... 171 8.1.1 Block Diagram....................171 Section 9 Clock Pulse Generator .................. 173 Overview........................... 173 9.1.1 Block Diagram....................173 9.1.2 Register Configuration..................173 Register Descriptions ......................
Page 8 10.4.2 Register Configuration..................198 10.4.3 Pin Functions ....................201 10.4.4 Pin States ......................203 10.5 Port 3..........................204 10.5.1 Overview ......................204 10.5.2 Register Configuration..................204 10.5.3 Pin Functions ....................208 10.5.4 Pin States ......................211 10.6 Port 4..........................212 10.6.1 Overview ......................
Page 9 11.3.3 Initializing the Counts..................252 Section 12 Timer B ......................253 12.1 Overview........................... 253 12.1.1 Features......................253 12.1.2 Block Diagram....................253 12.1.3 Pin Configuration ..................... 254 12.1.4 Register Configuration..................254 12.2 Register Descriptions ......................255 12.2.1 Timer Mode Register B (TMB) ................ 255 12.2.2 Timer Counter B (TCB)..................
Page 10 14.1.2 Block Diagram....................280 14.1.3 Register Configuration..................281 14.2 Register Descriptions ......................282 14.2.1 Timer L Mode Register (LMR) ................ 282 14.2.2 Linear Time Counter (LTC) ................284 14.2.3 Reload/Compare Match Register (RCR) ............284 14.2.4 Module Stop Control Register (MSTPCR)............285 14.3 Operation ..........................
Page 11 16.1.1 Features......................313 16.1.2 Block Diagram....................314 16.1.3 Pin Configuration ..................... 315 16.1.4 Register Configuration..................316 16.2 Register Descriptions ......................317 16.2.1 Free Running Counter (FRC) ................317 16.2.2 Output Comparing Registers A and B (OCRA and OCRB) ......318 16.2.3 Input Capture Registers A Through D (ICRA Through ICRD)......
Page 12 17.3.2 Interval Timer Operation .................. 356 17.3.3 Timing of Setting of Overflow Flag (OVF)............357 17.4 Interrupts........................... 358 17.5 Usage Notes ........................358 17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment ..................358 17.5.2 Changing Value of CKS2 to CKS0 ..............359 17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode ....
Page 13 20.2.3 Module Stop Control Register (MSTPCR)............384 20.3 14-Bit PWM Operation..................... 385 Section 21 Prescalar Unit ....................387 21.1 Overview........................... 387 21.1.1 Features......................387 21.1.2 Block Diagram....................388 21.1.3 Pin Configuration ..................... 389 21.1.4 Register Configuration..................389 21.2 Registers..........................390 21.2.1 Input Capture Register 1 (ICR1)...............
Page 14 22.3.4 Operation in Synchronous Mode ..............442 22.4 SCI Interrupts........................450 22.5 Usage Notes ........................451 Section 23 I C Bus Interface (IIC) ................. 459 23.1 Overview........................... 459 23.1.1 Features......................459 23.1.2 Block Diagram....................460 23.1.3 Pin Configuration ..................... 461 23.1.4 Register Configuration..................
Page 15 24.2.3 A/D Control Register (ADCR) ................. 518 24.2.4 A/D Control/Status Register (ADCSR) ............521 24.2.5 Trigger Select Register (ADTSR)..............524 24.2.6 Port Mode Register 0 (PMR0) ................524 24.2.7 Module Stop Control Register (MSTPCR)............525 24.3 Interface to Bus Master ..................... 526 24.4 Operation ..........................
Page 16 26.3.2 Block Diagram....................566 26.3.3 Register Configuration..................568 26.3.4 Register Description ..................569 26.3.5 Operation ......................574 26.4 HSW (Head-switch) Timing Generator ................589 26.4.1 Overview ......................589 26.4.2 Block Diagram....................589 26.4.3 HSW Timing Generator Configuration ............591 26.4.4 Register Configuration..................
Page 17 26.9.5 Operation ......................654 26.10 X-Value and Tracking Adjustment Circuit ............... 656 26.10.1 Overview ......................656 26.10.2 Block Diagram....................656 26.10.3 Register Description ..................658 26.11 Digital Filters ........................661 26.11.1 Overview ......................661 26.11.2 Block Diagram....................662 26.11.3 Arithmetic Buffer ..................... 664 26.11.4 Register Configuration..................
Page 18 26.15.6 Noise Detection ....................744 26.15.7 Activation of the Sync Signal Detector ............747 26.16 Servo Interrupt ........................748 26.16.1 Overview ......................748 26.16.2 Register Configuration..................748 26.16.3 Register Description ..................748 Section 27 Sync Separator for OSD and Data Slicer ..........
Page 19 28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)......... 807 28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4) ........808 28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4)......... 811 28.2.5 Module Stop Control Register (MSTPCR)............812 28.2.6 Monitor Output Setting Register (DOUT) ............
Page 20 29.5.9 Screen Control Register (DCNTL) ..............850 29.6 Other Settings........................855 29.6.1 TV Format ......................855 29.6.2 Display Data RAM Control ................855 29.6.3 Timing of OSD Display Updates Using Register Rewriting ......855 29.6.4 4fsc/2fsc......................855 29.6.5 OSDV Interrupts....................855 29.6.6 OSD Format Register (DFORM)..............
Page 21: Overview
30.2.7 OSD Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196....................896 30.3 Electrical Characteristics of HD64F2199 ................. 900 30.3.1 DC Characteristics of HD64F2199..............900 30.3.2 Allowable Output Currents of HD64F2199............907 30.3.3 AC Characteristics of HD64F2199..............908 30.3.4 Serial Interface Timing of HD64F2199............911 30.3.5 A/D Converter Characteristics of HD64F2199..........
Page 22: Section 1 Overview
CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. The H8S/2199 Series is equipped with a digital servo circuit, sync separator, OSD, data slicer, ROM, RAM, seven types of timers, three types of PWM, two types of serial communication interface, an I C bus interface, A/D converter, and I/O port as on-chip supporting modules.
Page 23 Table 1.1 Features of the H8S/2199 Series Item Specifications • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for real-time control  Maximum operating frequency: 10 MHz/4 to 5.5 V ...
Page 24 Item Specifications  Timer L Timer • 8-bit up/down counter • Clock source can be selected among 2 types of internal clock, CFG frequency division signal, and PB and REC-CTL (control pulse) • Compare-match clearing function/auto reload function  Timer R •...
Page 25 Item Specifications  Asynchronous mode or synchronous mode selectable Serial communication  Desired bit rate selectable with built-in baud rate generator interface (SCI)  Multiprocessor communication function  Conforms to Phillips I C bus interface C bus interface standard (2 channels) ...
Page 26  Sampling clock generated by AFC  Slice interrupt  Error detection  Flash memory or mask ROM (Refer to the product line-up) Memory  High-speed static RAM Product Name H8S/2199 128 k bytes 3 k bytes H8S/2198 112 k bytes 3 k bytes H8S/2197...
Page 27  Subclock pulse generator: 32.768 kHz  112-pin plastic QFP (FP-112) Packages Product lineup Product Code ROM/RAM Mask ROM F-ZTAT Series (bytes) Packages Versions Versions H8S/2199 HD6432199 HD64F2199 128 k/3 k FP-112 (256 k*/ 8 k*)  HD6432198 112 k/3 k FP-112  HD6432197...
Page 28: Internal Block Diagram
Internal Block Diagram Figure 1.1 shows an internal block diagram of the H8S/2199 Series. P37/TMO P27/SYNCI P36/BUZZ P26/SCL0 P35/PWM3 P25/SDA0 H8S/2000 CPU P34/PWM2 P24/SCL1 P33/PWM1 P23/SDA1 P32/PWM0 P22/SCK1 P31/SV2 Internal data bus P21/SO1 P30/SV1 P20/SI1 R O M Internal address bus...
Page 29: Pin Arrangement And Functions
Pin Arrangement and Functions 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8S/2199 Series. P32/PWM0 P31/SV2 P35/PWM3 P30/SV1 P36/BUZZ P70/PPG0 P37/TMO P71/PPG1 P60/RP0 P72/PPG2 P61/RP1 P73/PPG3 P62/RP2 P74/PPG4/RP8 P63/RP3 P75/PPG5/RP9 P64/RP4 P76/PPG6/RPA P65/RP5 P77/PPG7/RPB P66/RP6/ P80/YCO P67/RP7/TMBI...
Page 30: Pin Functions
1.3.2 Pin Functions Table 1.2 summarizes the functions of the H8S/2199 Series pins. Table 1.2 Pin Functions Type Symbol Pin No. Name and Function Power 56, 112 Input Power supply: supply All Vcc pins should be connected to the system...
Page 31 Type Symbol Pin No. Name and Function Operating Input Mode pin: mode This pin sets the operating mode. This pin control should not be changed while the MCU is in operation System Input Reset input: control When this pin is driven low, the chip is reset Input Flash memory enable: Enables/disables flash memory programming.
Page 32 Type Symbol Pin No. Name and Function ,546 Timers Input Timer R input capture: Input pin for input capture of Timer R TMRU-1 or TMRU-2 FTOA Output Timer X1 output compare A and B output: FTOB Output pin for output compare A and B of Timer FTIA Input Timer X1 input capture A, B, C and D input:...
Page 33 Type Symbol Pin No. Name and Function AN7 to 28 to 35 Input Analog input channels 7 to 0: converter Analog data input pins. A/D conversion is started by a software triggering Input Analog input channels 8, 9, A and B: Analog data input pins.
Page 34 Type Symbol Pin No. Name and Function Servo CTL Amp Output CTL amp output: circuits Output pin for CTL amp CTL SMT Input CTL Schmitt amp input: Input pin for CTL Schmitt amp CTLFB Input CLT feedback input: Input pin for CTL amp high-range characteristics control CTLREF Output...
Page 35 Type Symbol Pin No. Name and Function Sync Csync/ Input/ Sync signal input/output: separator Hsync output Composite sync signal input/output or horizontal sync signal input VLPF/ Input Sync signal input: Vsync Pin for connecting external LPF for vertical sync signal or input pin for vertical sync signal AFC pc Input/ AFC oscillation:...
Page 36 Type Symbol Pin No. Name and Function Output OSD digital output: Character data output Output OSD digital output: Character display position output Data CVin2 Input Composite video input: slicer Composite video signal input. Input 2-Vp-p composite video signal, and the sync tip of the signal is clamped to about 2.0 V.
Page 37: Cpu
Section 2 CPU Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16- bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
Page 38: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
16 ÷ 8-bit register-register divide: 1200 ns 16 × 16-bit register-register multiply: 2000 ns 32 ÷ 16-bit register-register divide: 2000 ns • Two CPU operating modes Normal mode*/Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available for this LSI.
Page 39: Differences From H8/300H Cpu
• Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing mode The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Page 40: Cpu Operating Modes
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area).
Page 41 (d) Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2.
Page 42 (e) Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack.
Page 43 (d) Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
Page 44 (e) Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack.
Page 45: Address Space
Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF...
Page 46: Register Configuration
Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR) 7 6 5 4 3 2 1 0 T –...
Page 47: General Registers
2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Page 48: Control Registers
Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
Page 49: Initial Register Values
Bit 6: User Bit or Interrupt Mask Bit (UI) Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, see section 6, Interrupt Controller.
Page 50: Data Formats
Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 51 Data Type General Register Data format Word data Word data Longword data [Legend] : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.11 General Register Data Formats (2) Rev.
Page 52: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.12 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 53: Instruction Set
Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer , PUSH LDM, STM MOVFPE, MOVTPE Arithmetic ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS...
Page 54: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Instruction — — — — — POP, PUSH — —...
Page 55: Table Of Instructions Classified By Function
2.6.3 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the functions of the instructions. The notation used in table 2.3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) (EAd) Destination operand (EAs)
Page 56 Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register MOVFPE Cannot be used in this LSI MOVTPE Cannot be used in this LSI @SP+ →...
Page 57 Table 2.4 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
Page 58 Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general...
Page 59 Table 2.5 Logic Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data...
Page 60 Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register 0 →...
Page 61 Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BOXR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C ⊕ [~ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in...
Page 62 Table 2.8 Branch Instructions Instruction Size* Function  Branches to a specified address if a specified condition is true The branching conditions are listed below Mnemonic Description Condition BRA (BT) Always (True) Always BRN (BF) Never (False) Never HIgh CVZ = 0 Low of Same CVZ = 1 BCC (BHS)
Page 63 Table 2.9 System Control Instructions Instruction Size* Function  TRAPA Starts trap-instruction exception handling  Returns from an exception-handling routine  SLEEP Causes a transition to a power-down state (EAs) → CCR, (EAs) → EXR Moves contents of a general register or memory or immediate data to CCR or EXR.
Page 64 Table 2.10 Block Data Transfer Instructions Instruction Size* Function  if R4L ≠ 0 then EEPMOV.B Repeat @ER5+→@er6+ R4L−1→R4L Until R4L = 0 else next;  if R4 ≠ 0 then EEPMOV.W Repeat @ER5+→@er6+ R4−1→R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6 R4L or R4: size of block (bytes)
Page 65: Basic Instruction Formats
2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.13 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc.
Page 66: Notes On Use Of Bit-Manipulation Instructions
2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0.
Page 67: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 68 (4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn (a) Register indirect with post-increment–@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
Page 69 (6) Immediate–#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.
Page 70: Effective Address Calculation
If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation...
Page 71 Table 2.13 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) 24 23 Don’t General register contents care Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) General register contents 24 23...
Page 72 Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Absolute address @aa:8 24 23 Don’t H'FFFF care @aa:16 24 23 16 15 Sign Don’t exten- care sion @aa:24 24 23 Don’t care @aa:32 24 23 Don’t care Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data Program-counter relative @(d:8, PC)/@(d:16, PC)
Page 73 Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Memory indirect @@aa:8 • Normal mode H'000000 24 23 16 15 Don’t H'00 care Memory contents • Advanced mode H'000000 24 23 Don’t Memory contents care Rev. 1.0, 02/00, page 53 of 1141...
Page 74: Processing States
Processing States 2.8.1 Overview The CPU has four main processing states: the reset state, exception-handling state, program execution state, and power-down state. Figure 2.15 shows a diagram of the processing states. Figure 2.16 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response...
Page 75: Reset State
Program execution state Sleep mode External interrupt request Exception-handling state Standby mode Power-down state = High Reset state Notes: From any state, a transition to the reset state occurs whenever goes low. A transition can also be made to the reset state when the watchdog timer overflows. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc.
Page 76: Exception-Handling State
2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions.
Page 77: Program Execution State
Figure 2.17 shows the stack after exception handling ends. Normal Mode Advanced Mode (24 bits) (16 bits) Notes: 1. Ignored when returning. 2. Normal mode is not available for this LSI. Figure 2.17 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence.
Page 78: Power-Down State
2.8.5 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode.
Page 79: Basic Timing
Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two states.
Page 80: On-Chip Supporting Module Access Timing
2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Bus cycle φ...
Page 81: Mcu Operating Modes
Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection This LSI has one operating mode (mode 1). This mode is selected depending on settings of the mode pin (MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MCU Operating Mode CPU Operating Mode Description...
Page 82: Register Descriptions
Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : — — — — — — — MDS0 Initial value : —* — R/W : — — — — — — Note: * Determined by MD0 pin MDCR is an 8-bit read-only register monitors the current operating mode of this LSI. Bit 7 to 1: Reserved.
Page 83: Operating Mode (Mode 1)
Bits 5 and 4    Interrupt control modes 1 and 0 (INTM1, INTM0) These bits are for selecting the interrupt control mode of the interrupt controller. For details of the interrupt control modes, see section 6.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 Bit 4 Interrupt...
Page 84: Address Map In Each Operating Mode
Address Map in Each Operating Mode H8S/2196 H8S/2197 H'000000 H'000000 Vector area Vector area H'0000FF On-chip ROM On-chip ROM (96 kbytes) (80 kbytes) H'007FFF H'013FFF H'017FFF H'040000 H'040000 OSD ROM OSD ROM (24 kbytes) (24 kbytes) H'045FFF H'045FFF H'FF8000 H'FFD000 H'FFD000 Internal I/O register Internal I/O register...
Page 85 H8S/2198 H8S/2199 H'000000 H'000000 Vector area Vector area On-chip ROM On-chip ROM (112 kbytes) (128 kbytes) H'01BFFF H'040000 H'01FFFF OSD ROM (24 kbytes) H'040000 H'045FFF OSD ROM (24 kbytes) H'045FFF H'FFD000 H'FFD000 Internal I/O register Internal I/O register H'FFD2FF H'FFD2FF...
Page 86: Power-Down State
Section 4 Power-Down State Overview In addition to the normal program execution state, this LSI has a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
Page 87 Table 4.1 H8S/2199 Series Internal States in Each Mode Medium- Module Function High-Speed Speed Sleep Stop Watch Sub-active Sub-sleep Standby System clock Functioning Functioning Functioning Functioning Halted Halted Halted Halted Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning...
Page 88 4. In the power-down mode, the analog section of the servo circuits are not turned off, therefore Vcc (Servo) current does not go low. When power-down is needed, externally shut down the analog system power. *1 The SCI1 status differs from the internal register. For details, refer to section 22, Serial Communication Interface 1.
Page 89 Table 4.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before State after Transition State after Return Transition SSBY TMA3 LSON DTON by SLEEP Instruction by Interrupt High-speed/ Sleep High-speed/ medium- medium-speed speed   Standby High-speed/ medium-speed ...
Page 90: Register Configuration
4.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR registers. Table 4.3 summarizes these registers. Table 4.3 Power-Down State Registers Name Abbreviation Initial Value Address* Standby control register SBYCR H'00 H'FFEA Low-power control register LPWRCR H'00 H'FFEB...
Page 91 Register Descriptions 4.2.1 Standby Control Register (SBYCR) Bit : SSBY STS2 STS1 STS0 — — SCK1 SCK0 Initial value : R/W : — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset. Bit 7...
Page 92 Bits 6 to 4    Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction.
Page 93: Low-Power Control Register (Lpwrcr)
4.2.2 Low-Power Control Register (LPWRCR) Bit : DTON LSON NESEL — — — Initial value : R/W : — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset. Bit 7...
Page 94 Bit 6    Low-Speed on Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared.
Page 95: Timer Register A (Tma)
4.2.3 Timer Register A (TMA) Bit : — — TMAOV TMAIE TMA3 TMA2 TMA1 TMA0 Initial value : R/W : R/(W)* Note: * Only 0 can be written, to clear the flag. The timer register A (TMA) controls timer A interrupts and selects input clock. Only bit 3 is explained here.
Page 96: Module Stop Control Register (Mstpcr)
4.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control. MSTPCR is initialized to H'FFFF by a reset.
Page 97: Medium-Speed Mode
Medium-Speed Mode When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The on- chip supporting modules other than the CPU always operate on the high-speed clock (φ).
Page 98: Sleep Mode
Sleep Mode 4.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU will enter sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained.
Page 99: Module Stop Mode
Module Stop Mode 4.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently.
Page 100: Standby Mode
Standby Mode 4.6.1 Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode will be entered.
Page 101 Table 4.5 Oscillation Settling Time Settings STS2 STS1 STS0 Standby Time 10 MHz 8 MHz Unit 8192 states 16384 states 32768 states 65536 states 131072 states 13.1 16.4 262144 states 26.2 32.8   µs Reserved Notes: * Don't care 1.
Page 102: Watch Mode
Watch Mode 4.7.1 Watch Mode If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU will make a transition to watch mode.
Page 103: Subsleep Mode
Subsleep Mode 4.8.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU will make a transition to subsleep mode.
Page 104: Subactive Mode
Subactive Mode 4.9.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the TMA3 bit in TMA (timer A) are all set to 1, the CPU will make a transition to subactive mode.
Page 105: Direct Transition
4.10 Direct Transition 4.10.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, medium-speed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program* is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
Page 106: Exception Handling
Section 5 Exception Handling Overview 5.1.1 Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 107: Exception Handling Operation
5.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3.
Page 108 Table 5.2 Exception Vector Table Exception Source Vector Number Vector Address Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 Direct transition H'0018 to H001B External interrupt H'001C to H'001F Trap instruction (4 sources) H'0020 to H'0023...
Page 109: Reset
Reset 5.2.1 Overview A reset has the highest exception priority. When the 5(6 pin goes low, all processing halts and the LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the 5(6 pin changes from low to high.
Page 110: Interrupts After Reset
Vector Internal Fetch of first program fetch processing instruction φ Internal address bus Internal read signal Internal write signal High level Internal data bus : Reset exception vector address ((1) = H'0000 or H'000000) : Start address (contents of reset exception vector address) : Start address ((3) = (2)) : First program instruction Figure 5.2 Reset Sequence (Mode 1)
Page 111: Interrupts
Interrupts Interrupt exception handling can be requested by six external sources (,548 to ,543) and internal sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI), A/D converter (ADC), I C bus interface (IIC), servo circuits, sync detection, data slicer, OSD,...
Page 112: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
Page 113: Stack Status After Exception Handling
Stack Status after Exception Handling Figures 5.4 and 5.5 show the stack after completion of trap instruction exception handling and interrupt exception handling. SP→ CCR* (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 5.4 Stack Status after Exception Handling (Normal Mode)* Note: * Normal mode is not available for this LSI.
Page 114: Notes On Use Of The Stack
Notes on Use of the Stack When accessing word data or longword data, this chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 115: Section 6 Interrupt Controller
Section 6 Interrupt Controller Overview 6.1.1 Features This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two Interrupt Control Modes  Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
Page 116: Block Diagram
6.1.2 Block Diagram Figure 6.1 shows a block diagram of the interrupt controller. INTM1, INTM0 SYSCR Interrupt request Vector number IRQ input IRQ input unit IRQR Priority determina- tion I, UI IEGR IENR Internal interrupt requests Interrupt controller [Legend] IEGR : IRQ edge select register IENR : IRQ enable register...
Page 117: Pin Configuration
6.1.3 Pin Configuration Table 6.1 summarizes the pins of the interrupt controller. Table 6.1 Interrupt Controller Pins Name Symbol Function ,543 External interrupt Input Maskable external interrupts; rising, falling, or both request 0 edges can be selected ,544 to External interrupt Input Maskable external interrupts: rising, or falling ,548...
Page 118 Register Descriptions 6.2.1 System Control Register (SYSCR) Bit : — — — INTM1 INTM0 XRST — — Initial value : — — — — — R/W : SYSCR is an 8-bit readable register that selects the interrupt control mode. Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, System Control Register (SYSCR).
Page 119: Interrupt Control Registers A To D (Icra To Icrd)
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) Bit : ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value : R/W : The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI.
Page 120: Irq Enable Register (Ienr)
6.2.3 IRQ Enable Register (IENR) Bit : IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E — — Initial value : — — R/W : IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IENR is initialized to H'00 by a reset. Bits 7 and 6...
Page 121: Irq Edge Select Registers (Iegr)
6.2.4 IRQ Edge Select Registers (IEGR) Bit : — IRQ5EG IRQ4EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0 Initial value : R/W : — IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins ,548 to ,543. IEGR register is initialized to H'00 by a reset.
Page 122: Irq Status Register (Irqr)
6.2.5 IRQ Status Register (IRQR) Bit : IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F — — Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W : — — Note: * Only 0 can be written, to clear the flag. IRQR is an 8-bit readable/writable register that indicates the status of I RQ 5 t o I RQ 0 i nt er r upt requests.
Page 123: Port Mode Register (Pmr1)
6.2.6 Port Mode Register (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is specified for each bit. PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Only bits 5 to 0 are explained here.
Page 124: Interrupt Sources
Interrupt Sources I nt er r upt s our ces com pr i s e ext er nal i nt er r upt s ( I RQ 5 t o I RQ 0) and i nt er nal i nt er r upt s . 6.3.1 External Interrupts Ther e ar e s i x ext er nal i nt er r upt s our ces ;...
Page 125: Internal Interrupts
Figure 6.3 shows the timing of IRQnF setting. Internal φ IRQn input pin IRQnF Figure 6.3 Timing of IRQnF Setting The vector num ber s f or I RQ 5 t o I RQ 0 i nt er r upt except i on handl i ng ar e 21 t o 26. U pon det ect i on of I RQ 5 t o I RQ 0 i nt er r upt s , t he appl i cabl e pi n i s s et i n t he por t r egi s t er 1 ( PM R1) as ,54Q pi n.
Page 126: Interrupt Exception Vector Table
6.3.3 Interrupt Exception Vector Table Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 6.4.
Page 127 Origin of Vector Priority Interrupt Source Interrupt Source Vector Address Remarks  High Address trap H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F ICRA6 HSW1 Servo circuit H'0050 to H'0053 ICRA5 IRQ0 External pin H'0054 to H'0057 ICRA4 IRQ1 H'0058 to H'005B...
Page 128 Origin of Vector Priority Interrupt Source Interrupt Source Vector Address Remarks High ICXA Timer X1 H'00B0 to H'00B3 ICRC7 ICXB H'00B4 to H'00B7 ICXC H'00B8 to H'00BB ICXD H'00BC to H'00BF OCX1 H'00C0 to H'00C3 OCX2 H'00C4 to H'00C7 OVFX H'00C8 to H'00CB VD interrupts Sync signal...
Page 129: Interrupt Operation
Interrupt Operation 6.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI* interrupts and address trap interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Page 130 Figure 6.4 shows a block diagram of the priority decision circuit. I C R Interrupt acceptance Default priority control and 3-level Vector number Interrupt source determination mask control Interrupt control modes 0 and 1 Figure 6.4 Block Diagram of Interrupt Priority Determination Operation •...
Page 131: Interrupt Control Mode 0
Table 6.7 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control, Interrupt Setting 3-Level Control Control Default Priority Mode INTM1 INTM0 Determination  ¡ ¡ ¡ ¡ Legend: ¡ : Interrupt operation control performed Used as interrupt mask bit Sets priority : Not used...
Page 132: Interrupt Control Mode 1
Program execution state Interrupt generated? Address trap interrupt? Hold pending Control level 1 interrupt? H S W 1 H S W 1 H S W 2 H S W 2 I = 0 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in...
Page 133 6.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR and ICR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1.
Page 134 (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending.
Page 135 Program execution state Interrupt generated? Address trap interrupt? Hold pending Control level 1 interrupt? H S W 1 H S W 1 H S W 2 H S W 2 I = 0 I = 0 UI = 0 Save PC and CCR I ←...
Page 136: Interrupt Exception Handling Sequence
6.4.4 Interrupt Exception Handling Sequence Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control 0 is set in advanced mode, and the program area and stack area are in on- chip memory. Figure 6.8 Interrupt Exception Handling Rev.
Page 137: Interrupt Response Times
6.4.5 Interrupt Response Times Table 6.8 shows interrupt response times-the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 6.8 are explained in table 6.9. Table 6.8 Interrupt Response Times Number of States Advanced Mode...
Page 138: Usage Notes
Usage Notes 6.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 139: Instructions That Disable Interrupts
6.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 140: Rom
Section 7 ROM Overview The H8S/2199 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2198 has 112 kbytes, the H8S/2197 has 96 kbytes, and the H8S/2196 has 80 kbytes*. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed.
Page 141: Overview Of Flash Memory
Overview of Flash Memory 7.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
Page 142: Block Diagram
: Flash memory control register 1 FLMCR2 : Flash memory control register 2 EBR1 : Erase block register 1 EBR2 : Erase block register 2 Figure 7.2 Block Diagram of Flash Memory (H8S/2199 Only) Rev. 1.0, 02/00, page 125 of 1141...
Page 143: Flash Memory Operating Modes
7.2.3 Flash Memory Operating Modes Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be read but not programmed or erased.
Page 144 On-Board Programming Modes • Boot mode 2. Writing control program transfer 1. Initial state The flash memory is in the erased state when the When boot mode is entered, the boot program in device is shipped. The description here applies to this LSI chip (originally incorporated in the chip) is the case where the old program version or data is started, and SCI communication check is carried...
Page 145 • User program mode 1. Initial state 2. Programming/erase control program transfer When the FWE pin is driven high, user software (1) The FWE assessment program that confirms that confirms this fact, executes the transfer program in the the FWE pin has been driven high, and (2) the flash memory, and transfers the programming/erase program that will transfer the programming/erase control program to RAM.
Page 146 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Block erase Programming control program* Program/program-verify Erase/erase-verify Program/program-verify Note: * To be provided by the user, in accordance with the recommended algorithm. Block Configuration The main ROM area is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks.
Page 147: Pin Configuration
7.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 7.1. Table 7.1 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 0 Input Sets this LSI operating mode Port 12...
Page 148: Flash Memory Register Descriptions
Flash Memory Register Descriptions 7.3.1 Flash Memory Control Register 1 (FLMCR1) SWE1 ESU1 PSU1 Initial value —* Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. With addresses H'00000 to H'3FFFF, program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the PV1 bit and EV1 bit.
Page 149 Bit 6    Software Write Enable (SWE): Enables or disables flash memory programming. SWE should be set before setting bits 5 to 0, bits 7 to 0 in EBR1, and bits 3 to 0 in EBR2. Bit 6 SWE1 Description Writes are disabled...
Page 150 Bit 3    Erase-Verify (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected Bit 2...
Page 151: Flash Memory Control Register 2 (Flmcr2)
7.3.2 Flash Memory Control Register 2 (FLMCR2) FLER SWE2 ESU2 PSU2 Initial value FLMCR2 is an 8-bit register used for flash memory operating control mode. With addresses H'40000 to H'47FFF, program-verify mode and erase-verify mode is entered by setting SWE2 when FWE (FLMCR1) = 1, then setting the EV2 bit and the PV2 bit. Program mode is entered by setting SWE2 when FWE (FLMCR1) = 1, then setting the SWE2 bit and PSU2 bit, and finally setting the P2 bit.
Page 152 Bit 6    Software Write Enable 2 (SWE2): Enables or disables flash memory programming (target address range: H'40000 to H'47FFF). SW2 should be set when setting bits 5 to 0 and bits 7 to 4 in EBR2. Bit 6 SWE2 Description Writes are disabled...
Page 153 Bit 2    Program-Verify 2 (PV2): Selects program-verify mode transition or clearing (target address range: H'40000 to H'47FFF). Do not set the ESU2, PSU2, EV2, E2, and P2 bits at the same time. Bit 2 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] Setting is available when FWE=1 and SWE2=1 are selected...
Page 154: Erase Block Register 1 (Ebr1)
7.3.3 Erase Block Register 1 (EBR1) EBR2 Initial value EBR1 is an 8-bit register that specify the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set.
Page 155: Serial/Timer Control Register (Stcr)
Table 7.3 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF...
Page 156 Bit 3    Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained.
Page 157: On-Board Programming Modes
On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 7.4.
Page 158: Boot Mode
7.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the LSI via the SCI.
Page 159 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment...
Page 160 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 7.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Page 161 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the TBD-byte area from TBD to TBD is reserved for use by the boot program, as shown in figure 7.10. The area to which the programming control program is transferred is TBD to TBD (TBD bytes). The boot program area can be used when the programming control program transferred into RAM enters the execution state.
Page 162 Notes on Use of Boot Mode: 1. When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input.
Page 163: User Program Mode
7.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Page 164: Programming/Erasing Flash Memory
Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. With addresses H'00000 to H'3FFFF, transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in FLMCR1.
Page 165: Program-Verify Mode
which the Pn bit is set is the flash memory programming time. Make a program setting for one programming operation using the table in the programming flowchart. 7.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
Page 166 Start Set SWE1 (2) bit in FLMCR(2) Wait 1 µs Store 128-byte program data in program data area and reprogram data area Programming pulse apply subroutine Enable WDT n= 1 m= 0 Set PSU1 (2) bit in FLMCR1 (2) Wait 50 µs Write 128-byte program data in RAM reprogram data area consecutevely to flash memory Set P1 (2) bit in FLMCR1 (2)
Page 167: Erase Mode (N = 1 When The Target Address Range Is H'00000 To H'3Ffff And N = 2 When The Target Address Range Is H'40000 To H'47Fff)
7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2 when the target address range is H'40000 to H'47FFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 7.13.
Page 168 START Set SWE bit in FLMCR1 Wait 1 µs n = 1 Set EBR1 (2) Enable WDT Set ESU1 (2) bit in FLMCR1 (2) Wait 100 µs Start of erase Set E1 (2) bit in FLMCR1 (2) Wait 10 ms Halt erase Clear E1 (2) bit in FLMCR1 (2) Wait 10 µs...
Page 169: Erase-Verify Mode (N = 1 When The Target Address Range Is H'00000 To H'3Ffff And N = 2 When The Target Address Range Is H'40000 To H'47Fff)
7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2 when the target address range is H'40000 to H'47FFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased.
Page 170: Flash Memory Protection
Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 7.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2).
Page 171: Software Protection
7.6.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1 and SWE2 bit in FLMCR2 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1) or P2 or E2 bit in flash memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode.
Page 172: Error Protection
7.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
Page 173: Interrupt Handling When Programming/Erasing Flash Memory
Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMR2), and while the boot program is executing in boot mode , to give priority to the program or erase operation.
Page 174: Flash Memory Writer Mode
Figure 7.15 shows the memory map in writer mode. Table 7.8 Socket Adapter Product Codes Product Codes Package Socket Adapter Product Code HD64F2199 112-pin QFP H8S/2199 MCU mode Writer mode H'000000 H'00000 On-chip ROM area H'47FFF H'47FFF Figure 7.15 Memory Map in Writer Mode...
Page 175: Writer Mode Operation
7.8.3 Writer Mode Operation Table 7.9 shows how the different operating modes are set when using writer mode, and table 7.10 lists the commands used in writer mode. Details of each mode are given below. • Memory Read Mode: Memory read mode supports byte reads. •...
Page 176: Memory Read Mode
7.8.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. •...
Page 177 Table 7.12 AC Characteristics when Entering Another Mode from Memory Read Mode − − − − Preliminary − − − − = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Command write cycle nxtc...
Page 178 − − − − Preliminary − − − − Table 7.13 AC Characteristics in Memory Read Mode (2) = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Access time ...
Page 179: Auto-Program Mode
7.8.5 Auto-Program Mode AC Characteristics − − − − Preliminary − − − − Table 7.14 AC Characteristics in Auto-Program = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Command write cycle nxtc ...
Page 180 A18 to A0 ADDRESS STABLE nxtc nxtc Data transfer wsts 1 byte to 128 bytes (1 to 3,000 ms) write Programming operation end identification signal Programming normal end identification signal Programming wait H'40 DATA DATA IO5 to IO0 H'00 Figure 7.20 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode •...
Page 181: Auto-Erase Mode
7.8.6 Auto-Erase Mode AC Characteristics − − − − Preliminary − − − − Table 7.15 AC Characteristics in Auto-Erase Mode = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Command write cycle nxtc...
Page 182: Status Read Mode
Notes on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking IO6. Alternatively, status read mode can also be used for this purpose (IO7 status polling uses the auto-erase operation end identification pin).
Page 183 A18 to A0 nxtc nxtc nxtc H'71 H'71 IO7 to IO0 DATA Note: IO2 and IO3 are undefined. Figure 7.22 Status Read Mode Timing Waveforms Table 7.17 Status Read Mode Return Commands Pin Name IO3 IO2 IO1   Attribute Normal end Command Programming...
Page 184: Status Polling
7.8.8 Status Polling The IO7 status polling flag indicates the operating status in auto-program or auto-erase mode. The IO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 7.18 Status Polling Output Truth Table Internal Operation ...
Page 185: Writer Mode Transition Time
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 186: Notes When Converting The F-Ztat Application Software To The Mask-Rom Versions
Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM of the mask-ROM version and F–ZTAT version differ as follows.
Page 187: Ram
The H8S/2199, H8S/2198, H8S/2197, and H8S/2196 have 3 kbytes of on-chip high-speed static RAM, and the H8S/2199 F-ZTAT has 8 kbytes. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer.
Page 188: Clock Pulse Generator
Section 9 Clock Pulse Generator Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
Page 189: Register Descriptions
Register Descriptions 9.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — SCK1 SCK0 Initial value — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby Control Register (SBYCR).
Page 190: Low-Power Control Register (Lpwrcr)
9.2.2 Low-Power Control Register (LPWRCR) DTON LSON NESEL — — — Initial value — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, Low- Power Control Register (LPWRCR).
Page 191: Oscillator
Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 9.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 9.2. An AT-cut parallel-resonance crystal should be used. OSC1 = 10 to 22pF L1 =...
Page 192 Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 9.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins.
Page 193: External Clock Input
9.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 9.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode.
Page 194 External Clock: The external clock signal should have the same frequency as the system clock (φ). Table 9.3 and figure 9.6 show the input conditions for the external clock. Table 9.3 External Clock Input Conditions = 4.0 to 5.5 V Item Symbol Unit...
Page 195 Table 9.4 External Clock Output Settling Delay Time Conditions: V = 4.0 V to 5.5 V, AV = 4.0 V to 5.5 V, V = AV = 0 V Item Symbol Unit Notes  µs External clock output settling Figure 9.7 DEXT delay time of 5(6 pulse width (t...
Page 196: Duty Adjustment Circuit
Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). Medium-Speed Clock Divider The medium-speed divider divides the system clock to generate φ/16, φ/32, and φ/64 clocks. Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/16, φ/32 or φ/64) to be supplied to the bus master (CPU), according to the settings of bits...
Page 197: Subclock Oscillator Circuit
Subclock Oscillator Circuit 9.7.1 Connecting 32.768 kHz Crystal Resonator When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in figure 9.8. For precautions on connecting, see Note on Board Design, in section 9.3.1 Connecting a Crystal Resonator.
Page 198: When Subclock Is Not Needed
9.7.2 When Subclock is not Needed Connect X1 pin to V , and X2 pin should remain open as shown in figure 9.10. Open Figure 9.10 Terminal When Subclock is not Needed Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a clock obtained by dividing the φ...
Page 199: Section 10 I/O Port
Section 10 I/O Port 10.1 Overview 10.1.1 Port Functions This LSI has seven 8-bit I/O ports (including one CMOS high-current port), and one 8-bit input port. Table 10.1 shows the functions of each port. Each I/O part a port control register (PCR) that controls an input and output and a port data register (PDR) for storing output data.
Page 200 Table 10.1 Port Functions Function Switching Port Description Pins Alternative Functions Register Port 0 P07 to P00 input- P07/AN7 to Analog data input channels 7 to 0 PMR0 only ports P00/AN0 Port 1 P17 to P10 I/O ports P17/TMOW Prescalar unit frequency division clock PMR1 (Built-in MOS pull-up output...
Page 201 Function Switching Port Description Pins Alternative Functions Register Port 8 P87 to P80 I/O ports P87/DPG PMR8 DPG signal input PMRC P86/EXTTRG External trigger signal input P85/COMP/B Pre-amplifier output result signal input Color signal output (B) P84/H.AMP Pre-amplifier output select signal SW/G input Color signal output (G)
Page 202: Mos Pull-Up Transistors
10.1.3 MOS Pull-Up Transistors The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the pin function is set to an input by PCR1 to PCR3.
Page 203: Port 0
10.2 Port 0 10.2.1 Overview Port 0 is an 8-bit input-only port. Table 10.2 shows the port 0 configuration. Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input channels (AN7 to AN0). It is switched by port mode register 0 (PMR0). Table 10.2 Port 0 Configuration Port Function...
Page 204: Register Configuration
10.2.2 Register Configuration Table 10.3 shows the port 0 register configuration. Table 10.3 Port 0 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 0 PMR0 Byte H'00 H'FFCD  Port data register 0 PDR0 Byte H'FFC0 Note: * Lower 16 bits of the address. (1) Port Mode Register 0 (PMR0) Bit : PMR07...
Page 205: Pin Functions
(2) Port Data Register 0 (PDR0) PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00 Initial value : — — — — — — — — R/W : Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0 (general input port), the pin state is read if PDR0 is read.
Page 206: Port 1
10.3 Port 1 10.3.1 Overview Port 1 is an 8-bit I/O port. Table 10.5 shows the port 1 configuration. Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division clock output (TMOW), input capture input (,&), or external interrupt request inputs (,548 to ,543).
Page 207 Port Mode Register 1 (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register.
Page 208 Bit 7    P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used as a P17 I/O pin or a TMOW pin for the frequency division clock output. Bit 7 PMR17 Description The P17/TMOW pin functions as a P17 I/O pin (Initial value) The P17/TMOW pin functions as a TMOW output pin Bit 6...
Page 209 Bits 7 to 0    P17 to P10 Pin Switching (PCR17 toPCR10) Bit n PCR1n Description The P1n pin functions as an input pin (Initial value) The P1n pin functions as an output pin (n = 7 to 0) Port Data Register 1 (PDR1) Bit : PDR17...
Page 210: Pin Functions
10.3.3 Pin Functions This section describes the port 1 pin functions and their selection methods. P17/TMOW: P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and the PCR17 bit in PCR1. PMR17 PCR17 Pin Function P17 input pin P17 output pin TMOW output pin Note: * Don’t care...
Page 211 10.3.4 Pin States Table 10.7 shows the port 1 pin states in each operation mode. Table 10.7 Port 1 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P17/TMOW High- Operation Holding High- High- Operation Holding P16/,& impedance impedance impedance P15/,548 P10/,543...
Page 212: Port 3
10.4 Port 2 10.4.1 Overview Port 2 is an 8-bit I/O port. Table 10.8 shows the port 2 configuration. Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O (SCK1), receive data input (SI1), send data output (SO1), I C bus interface clock I/O (SCL0, SCL1), or data I/O (SDA0, SDA1).
Page 213 Port Control Register 2 (PCR2) Bit : PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Initial value : R/W : Port control register 2 (PCR2) controls the I/Os of pins P27 to P20 of port 2 in a unit of bit. When PCR2 is set to 1, the corresponding P27 to P20 pins become output pins, and when it is set to 0, they become input pins.
Page 214 MOS Pull-Up Select Register 2 (PUR2) Bit : PUR27 PUR26 PUR25 PUR24 PUR23 PUR22 PUR21 PUR20 Initial value : R/W : MOS pull-up selector register 2 (PUR2) controls the ON and OFF of the MOS pull-up transistor of port 2. Only the pin whose corresponding bit of PCR2 was set to 0 (input) becomes valid. If the corresponding bit of PCR2 is set to 1 (output), the corresponding bit of PUR2 becomes invalid and the MOS pull-up transistor is turned off.
Page 215: Pin Functions
10.4.3 Pin Functions This section describes the port 2 pin functions and their selection methods. P27/SYNCI: P27/SYNCI is switched as shown below according to the PCR27 bit in PCR2. Pin Function P27 input pin P27 output pin Note: Because the SYNCI always functions, the alternative pin need always be set to the high or low level regardless of active mode or low power consumption mode.
Page 216 P23/SDA1: P23/SDA1 is switched as shown below according to the PCR23 bit in PCR2 and the II1CE bit in the I C Bus control register (ICCR1). II1CE PCR23 Pin Function P23 input pin P23 output pin SDA1 I/O pin Note: * Don’t care P22/SCK1: P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/$ bit in SMR, and the CKE1 and CKE0 bits in SCR.
Page 217: Pin States
10.4.4 Pin States Table 10.10 shows the port 2 pin states in each operation mode. Table 10.10 Port 2 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P27/SYNCI High- Operation Holding High- High- Operation Holding P26/SCL0 impedance impedance impedance P25/SDA0 P24/SCL1...
Page 218: Port 4
10.5 Port 3 10.5.1 Overview Port 3 is an 8-bit I/O port. Table 10.11 shows the port 3 configuration. Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer output (TMO), buzzer output (BUZZ), 8-bit PWM outputs (PWM3 to PWM0), SCI2 strobe output (STRB), or chip select input (&6).
Page 219 Port Mode Register 3 (PMR3) Bit : PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Initial value : R/W : Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is specified in a unit of bit. PMR3 is an 8-bit read/write enable register.
Page 220 Bits 5 to 2    P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): PMR35 to PMR32 set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM output. Bit n PMR3n Description The P3n/PWMm pin functions as a P3n I/O pin...
Page 221 Port Control Register 3 (PCR3) Bit : PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 Initial value : R/W : Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit. When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set to 0, they become input pins.
Page 222: Pin Functions
MOS Pull-Up Select Register 3 (PUR3) Bit : PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30 Initial value : R/W : MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If the corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid and the MOS pull-up transistor is turned off.
Page 223 P36/BUZZ: P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the PCR36 bit in PCR3. PMR36 PCR36 Pin Function P36 input pin P36 output pin BUZZ output pin Note: * Don’t care P35/PWM3: P35/PWM3 is switched as shown below according to the PMR3n bit in PMR3 and the PCR3n bit in PCR3.
Page 224 P32/PWM0: P32/PWM0 is switched as shown below according to the PMR32 bit in PMR3 and the PCR32 bit in PCR. PMR32 PCR32 Pin Function P32 input pin P32 output pin PWM0 output pin P31/SV2: P31/SV2 is switched as shown below according to the PMR31 bit in PMR3 and the PCR31 bit in PCR3.
Page 225: Pin States
10.5.4 Pin States Table 10.13 shows the port 3 pin states in each operation mode. Table 10.13 Port 3 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P37/TMO High- Operation Holding High- High- Operation Holding P36/BUZZ impedance impedance impedance P35/PWM3 P32/PWM0...
Page 226 10.6 Port 4 10.6.1 Overview Port 4 is an 8-bit I/O port. Table 10.14 shows the port 4 configuration. Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output (PWM14).
Page 227 Port Mode Register 4 (PMR4) Bit : PMR40 PMR47 — — — — — — Initial value : R/W : — — — — — — Port mode register 4 (PMR4) controls switching of the P47/RPTRG pin and the P40/PWM14 pin function.
Page 228 Port Control Register 4 (PCR4) Bit : PCR47 PCR46 PCR45 PCR44 PCR43 PCR42 PCR41 PCR40 Initial value : R/W : Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit. When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set to 0, they become input pins.
Page 229 10.6.3 Pin Functions This section describes the port 4 pin functions and their selection methods. P47/RPTRG: P47/RPTRG is switched as shown below according to the PMR47 bit in PMR4 and the PMR47 bit in PMR4 and the PCR47 bit in PCR4. PMR47 PCR47 Pin Function...
Page 230 P43/FTIC: P43/FTIC is switched as shown below according to the PCR43 bit in PCR4. PCR43 Pin Function P43 input pin FTIC input pin P43 output pin P42/FTIB: P42/FTIB is switched as shown below according to the PCR42 bit in PCR4. PCR42 Pin Function P42 input pin...
Page 231 10.6.4 Pin States Table 10.16 shows the port 4 pin states in each operation mode. Table 10.16 Port 4 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep High- Operation Holding High- High- Operation Holding P46/FTOB impedance impedance impedance P45/FTOA P44/FTID P43/FTIC...
Page 232: Port 6
10.7 Port 6 10.7.1 Overview Port 6 is an 8-bit I/O port. Table 10.17 shows the port 6 configuration. Port 6 is a large current I/O port. The synchronous current is 20 mA maximum (VOL=1.5 V) and four pins can be turned on at the same time.
Page 233: Register Configuration
10.7.2 Register Configuration Table 10.18 shows the port 6 register configuration. Table 10.18 Port 6 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 6 PMR6 Byte H'00 H'FFDD Port mode register A PMRA Byte H'3F H'FFD9 Port control register 6 PCR6 Byte H'00...
Page 234 Port Mode Register A (PMRA) Bit : PMRA7 PMRA6 — — — — — — Initial value : R/W : — — — — — — Port mode register A (PMRA) switches the pin functions in port 6. Switching is specified in a unit of bit.
Page 235 Port Control Register 6 (PCR6) Bit : PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial value : R/W : Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output in a unit of bit together with PMR6. When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to 1, and they become general input pins if it is set to 0.
Page 236 Realtime Output Trigger Select Register (RTPSR1) Bit : RTPSR17 RTPSR16 RTPSR15 RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10 Initial value : R/W : The realtime output trigger select register (RTPSR1) sets whether the external trigger (RPTRG pin input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of bit.
Page 237 Real Time Output Trigger Edge Select Register (RTPEGR) Bit : — — — — — — RTPEGR1 RTPEGR0 Initial value : R/W : — — — — — — The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external or internal trigger input for the realtime output.
Page 238 10.7.3 Pin Functions This section describes the port 6 pin functions and their selection methods. P67/RP7/TMBI: P67/RP7/TMBI is switched as shown below according to the PMRA7 bit in PMRA, PMR67 bit in PMR6, and PCR67 bit in PCR6. Value When PDR6n PMRA7 PMR67 PCR67...
Page 239: Pin Functions
P65/RP5 to P60/RPD: P65/RP5 to P60/RPD are switched below according to the PMRAn bit in PMRA, PMR6n bit in PMR6, and PCR6n bit in PCR6. PMR6n PCR6n Pin Function Output Value Value When PDR6n Was Read  P6n input pin P6n pin P6n output pin PDR6n...
Page 240: Operation
10.7.4 Operation Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6 functions as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The operation per port 6 function is shown below.
Page 241: Pin States
• Operation of the Realtime Output Port (PMR6 = 1) When PMR6 is 1, it operates as a realtime output port. When a trigger is input, the PDR6 data is transferred to PDRS6 and the PCR6 is transferred data to PCRS6, respectively. In this case, when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin.
Page 242: Port 7
10.8 Port 7 10.8.1 Overview Port 7 is an 8-bit I/O port. Table 10.20 shows the port 7 configuration. Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0). It is switched by port mode register 7 (PMR7) and port control register 7 (PCR7).
Page 243: Register Configuration
10.8.2 Register Configuration Table 10.21 shows the port 7 register configuration. Table 10.21 Port 7 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 7 PMR7 Byte H'00 H'FFDE Port mode register B PMRB Byte H'0F H'FFDA Port control register 7 PCR7 Byte H'00...
Page 244 Port Mode Register 7 (PMR7) Bit : PMR77 PMR76 PMR75 PMR74 PMR73 PMR72 PMR71 PMR70 Initial value : R/W : Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is specified in a unit of bit. PMR7 is an 8-bit read/write enable register.
Page 245 Bits 7 to 4    P77/RP7B to P74/RP8 Pin Switching (PMRB7 to PMRB4): P77/RP7B to P74/RP8 set whether the P7n/RPm pin is used as a P7n I/O pin or a RPm pin for the realtime output port. (n= 7 to 4 and m= B, A, 9, or 8) Bit n PMRBn Description...
Page 246 Port Data Register 7 (PDR7) Bit : PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70 Initial value : R/W : Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7. If PCR7 is 1 (output) when PMRB=0, the PDR7 values are directly read when port 7 is read. Accordingly, the pin states are not affected.
Page 247 Bits 7 to 4    RPB to RP8 Pin Trigger Switching (RTPSR27 to RTPSR24) Bit7 RTPSR2n Description Selects external trigger (RPTRG pin input) for trigger input (Initial value) Selects internal trigger (HSW) for trigger input (n = 7 to 4) Realtime Output Trigger Edge Selection Register (RTPEGR) Bit : —...
Page 248: Pin Functions
10.8.3 Pin Functions This section describes the port 7 pin functions and their selection methods. P77/PPG7/RPB to P74/PPG4/RP8: P77/PPG7/RPB to P74/PPG4/RP8 are switched as shown below according to the PMRBn bit in PMRB and the PCR7n bit in PCR7. Value Returned when PMRBn PMR7n PCR7n...
Page 249: Operation
10.8.4 Operation Port 7 can be used by the PMRB as a realtime output port or an I/O port. Port 7 functions as a realtime output port when PMRB=1 and functions as an I/O port when PMRB=0. Figure 10.3 show the block diagram of port 7. Internal trigger HSW RTPEGR write...
Page 250: Pin States
Port 7 functions as follows: 1. Realtime output port function (PMRB=1) Port function as a realtime output port when PMRB is 1. After a trigger input, the PDR7 data is transferred to PDRS7 and PCR7 data is transferred to PCRS7. In this case, when PCRS7 is 1, the PDRS7 data of the corresponding bit is output from the RP pin.
Page 251: Port 8
10.9 Port 8 10.9.1 Overview Port 8 is an 8-bit I/O port. Table 10.23 shows the port 8 configuration. Port 8 consists of pins that are used both as standard-current I/O ports (P87 to P80) and an external CTL signal input (EXCTL), a pre-amplifier output result signal input (COMP), color signal outputs (R, G, and B), a pre-amplifier output selection signal output (H.Amp SW), a control signal output for processing color signal (C.Rotary), a DPG signal input (DPG), a capstan external sync signal input (EXCAP), an OSD character display position output (YB0), an OSD character data...
Page 252: Register Configuration
10.9.2 Register Configuration Table 10.24 shows the port 8 register configuration. Table 10.24 Port 8 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 8 PMR8 Byte H'00 H'FFDF Port mode register C PMRC Byte H'C5 H'FFE0 Port control register 8 PCR8 Byte H'00...
Page 253 Port Mode Register 8 (PMR8) Bit : PMR87 PMR86 PMR85 PMR84 PMR83 PMR82 PMR81 PMR80 Initial value : R/W : Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is specified in a unit of bit. PMR8 is an 8-bit read/write enable register.
Page 254 Bit 4    P84/H.Amp SW Pin Switching (PMR84): PMR84 sets whether the P84/H.Amp SW pin is used as a P84 I/O pin or H.Amp SW pin of the preamplifier output select signal output. Bit 4 PMR84 Description P84/H.Amp SW pin functions as a P84 I/O pin (Initial value) P84/H.Amp SW pin functions as a H.Amp SW output pin Bit 3...
Page 255 Port Mode Register C (PMRC) Bit : — — PMRC5 PMRC4 PMRC3 — PMRC1 — Initial value : R/W : — — — — Port mode register C (PMRC) controls switching of each pin function of port 8. The switching is specified in a unit of a bit.
Page 256 Bit 1    P81/YB0 Pin Switching (PMRC1): PMRC1 sets whether to use the P81/YB0 pin as a P81 I/O pin or a YB0 pin of the OSD character display position output. Bit7 PMR1 Description P81/YB0 pin functions as a P81 I/O pin (Initial value) P81/YB0 pin functions as a YB0 output pin Port Control Register 8 (PCR8)
Page 257 Port Data Register 8 (PDR8) Bit : PDR87 PDR86 PDR85 PDR784 PDR83 PDR82 PDR81 PDR80 Initial value : R/W : Port data register 8 (PDR8) stores the data of pins P87 to P80 port 8. When PCR is 1 (output), the pin states are read is port 8 is read.
Page 258: Pin Functions
10.9.3 Pin Functions This section describes the port 8 pin functions and their selection methods. P87/DPG: P87/DPG is switched as shown below according to the PMR87 bit in PMR8 and PCR87 bit in PCR8. PMR87 PCR87 Pin Function P87 input pin P87 output pin DPG input pin P86/EXTTRG: P86/EXTTRG is switched as shown below according to the PMR86 bit in PMR8...
Page 259 P83/C.Rotary/R: P83/C.Rotary/R is switched as shown below according to the PMR83bit in PMR8, PMRC3 bit in PMRC, and PCR83 bit in PCR8. PMRC3 PMR83 PCR83 Pin Function P83 input pin P83 output pin C.Rotary output pin R output pin P82/EXCTL: P82/EXCTL is switched as shown below according to the PMR82 bit in PMR8 and PCR82 bit in PCR8.
Page 260: Pin States
10.9.4 Pin States Table 10.25 shows the port 8 pin states in each operation mode. Table 10.25 Port 8 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P87/DPG High- Operation Holding High- High- Operation Holding P86/ impedance impedance impedance EXTTRG P85/COMP/...
Page 261: Section 11 Timer A
Section 11 Timer A 11.1 Overview Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz crystal oscillator. 11.1.1 Features Features of timer A are as follows: • Choices of eight different types of internal clocks (φ/16384, φ/8192, φ/4096, φ/1024, φ/512, φ/256, φ/64 and φ/16) are available for your selection.
Page 262: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of timer A. 32 kHz Prescaler W φw Crystal oscillator (PSW) φw/128 Overflowing of φ/16384, φ/8192, the interval timer φ/4096, φ/1024, φ/512, φ/256, φ/64, φ/16 Prescaler S System φ Interrupting (PSS) clock Interrupt circuit...
Page 263: Register Descriptions
11.2 Register Descriptions 11.2.1 Timer Mode Register A (TMA) Bit : — — TMAOV TMAIE TMA3 TMA2 TMA1 TMA0 Initial value : — — R/W : R/(W)* Note: * Only 0 can be written to clear the flag. The timer mode register A (TMA) works to control the interrupts of timer A and to select the input clock.
Page 264 Bit 3    Selection of the Clock Source and Prescaler (TMA3): This bit works to select the PSS or PSW as the clock source for the Timer A. Bit 3 TMA3 Description Selects the PSS as the clock source for the Timer A (Initial value) Selects the PSW as the clock source for the Timer A Bits 2 to 0...
Page 265: Timer Counter A (Tca)
11.2.2 Timer Counter A (TCA) Bit : TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value : R/W : The timer counter A (TCA) is an 8-bit up-counter that counts up on inputs from the internal clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA When the TCA overflows, the TMAOV bit of the TMA is set to 1.
Page 266: Operation
11.3 Operation Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz crystal oscillator. 11.3.1 Operation as the Interval Timer When the TMA3 bit of the TMA is cleared to 0, timer A works as an 8-bit interval timer. After reset, the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues counting up as the interval counter without interrupts right after resetting.
Page 267: Section 12 Timer B
Section 12 Timer B 12.1 Overview Timer B is an 8-bit up-counter. Timer B is equipped with two different types of functions namely, the interval function and the auto reloading function. 12.1.1 Features • Seven different types of internal clocks (φ/16384, φ/4096, φ/1024, φ/512, φ/128, φ/32 and φ/8) or an of external clock can be selected.
Page 268: Pin Configuration
12.1.3 Pin Configuration Table 12.1 shows the pin configuration of timer B. Table 12.1 Pin Configuration Name Abbrev. Function Event inputs to timer B TMBI Input Event input pin for inputs to the TCB 12.1.4 Register Configuration Table 12.2 shows the register configuration of timer B. The TCB and TLB are being allocated to the same address.
Page 269 12.2 Register Descriptions 12.2.1 Timer Mode Register B (TMB) Bit : — — TMB17 TMBIF TMBIE TMB12 TMB11 TMB10 Initial value : R/W : R/(W)* — — Note: * Only 0 can be written to clear the flag. The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto reloading function and to select the input clock.
Page 270 Bit 5    Enabling Interrupt of the Timer B (TMBIE): This bit works to permit/prohibit occurrence of interrupt of timer B when the TCB overflows and when the TMBIF is set to 1. Bit 5 TMBIE Description Prohibits interrupt of timer B (Initial value) Permits interrupt of timer B Bits 4 and 3...
Page 271: Timer Counter B (Tcb)
12.2.2 Timer Counter B (TCB) Bit : TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 Initial value : R/W : The TCB is an 8-bit readable register which works to count up by the internal clock inputs and external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB. When the TCB overflows (H'FF →...
Page 272: Port Mode Register A (Pmra)
12.2.4 Port Mode Register A (PMRA) Bit : — — — PMRA7 PMRA6 — — — Initial value : — — — — — — R/W : The port mode register A (PMRA) works to changeover the pin functions of the port 6 and to designate the edge sense of the event inputs of timer B (TMBI).
Page 273: Module Stop Control Register (Mstpcr)
12.2.5 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 274: Operation
12.3 Operation 12.3.1 Operation as the Interval Timer When the TMB17 bit of the TMB is set to 0, timer B works as an 8-bit interval timer. When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, timer B continues counting up as the interval timer without interrupts right after resetting.
Page 275: Section 13 Timer J
Section 13 Timer J 13.1 Overview Timer J consists of twin counters. It carries different operation modes such as reloading and event counting. 13.1.1 Features Timer J consists of an 8-bit reloading timer and an 8-bit/16-bit selectable reloading timer. It has various functions as listed below.
Page 276 BUZZ REMOout Toggle Edge detection Toggle 8/16 Reloading register Synchronization PS11,10 Figure 13.1 Block Diagram of timer J Rev. 1.0, 02/00, page 262 of 1141...
Page 277: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the pin configuration of timer J. Table 13.1 Pin Configuration Name Abbrev. Function ,544 Event input pin Input Event inputs to the TMJ-1 ,545 Event input pin Input Event inputs to the TMJ-2 13.1.4 Register Configuration Table 13.2 shows the register configuration of timer J.
Page 278 13.2 Register Descriptions 13.2.1 Timer Mode Register J (TMJ) Bit : PS11 PS10 8/16 PS21 PS20 Initial value : R/W : The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and to set the operation mode. The TMJ is an 8-bit register and bit 1 is for read only.
Page 279 Bit 5    Starting the Remote Controlled Operation (ST): This bit works to start the remote controlled operations. When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions. When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be valid under the remote controlling mode, namely, when bit 0 (T/R bit) is 1 and bit 4 (8/16 bit) is 0.
Page 280 Bit 0    Switching Over Between Timer Output/Remote Controlling Output (T/R): This bit works to select if using the timer outputs from the TMJ-1 as the output signal through the TMO pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the output signal through the TMO pin.
Page 281: Timer J Control Register (Tmjc)
13.2.2 Timer J Control Register (TMJC) Bit : PS22 BUZZ1 BUZZ0 MON1 MON0 TMJ2IE TMJ1IE Initial value : R/W : The timer J control register (TMJC) works to select the buzzer output frequency and to control permission/prohibition of interrupts. The TMJC is an 8-bit read/write register. When reset, the TMJC is initialized to H'09.
Page 282 Bits 5 and 4    Selecting the Monitor Signals (MON1 or MON0): These bits work to select the type of signals being output through the BUZZ pin for monitoring purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 10. When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
Page 283 Bit 1    Enabling Interrupt of the TMJ1I (TMJ1IE): This bit works to permit/prohibit occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I. Bit 1 TMJ1IE Description Prohibits occurrence of TMJ1I interrupt (Initial value) Permits occurrence of TMJ1I interrupt Bit 0...
Page 284: Timer J Status Register (Tmjs)
13.2.3 Timer J Status Register (TMJS) Bit : TMJ2I TMJ1I — — — — — — Initial value : — — — — — — R/(W)* R/(W)* R/W : Note: * Only 0 can be written to clear the flag. The timer J status register (TMJS) works to indicate issuance of the interrupt request of timer J.
Page 285: Timer Counter J (Tcj)
13.2.4 Timer Counter J (TCJ) Bit : TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 Initial value : R/W : The timer counter J (TCJ) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and PS10 bits of the TMJ.
Page 286: Timer Load Register J (Tlj)
13.2.6 Timer Load Register J (TLJ) Bit : TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10 Initial value : R/W : The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading value of the TCJ. When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and the TCJ starts counting down from the set value.
Page 287: Module Stop Control Register (Mstpcr)
13.2.8 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP13 bit is set to 1, timer J stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 288: Operation
13.3 Operation 13.3.1 8-bit Reload Timer (TMJ-1) The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through the ,544 pin are being used. By selecting the edge signals through the ,544 pin, it can also be used as an event counter.
Page 289: Remote Controlled Data Transmission
information on the 16-bit or 24-bit reload timer, see section 13.3.1, 8-bit Reload Timer (TMJ-1). The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission. Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data Transmission.
Page 290 Figure 13.3 Timer Output Timing Rev. 1.0, 02/00, page 276 of 1141...
Page 291 When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote controlled data transmission starts.
Page 292: Tmj-2 Expansion Function
13.3.4 TMJ-2 Expansion Function The TMJ-2 expansion function is enabled by setting the EXN bit in the timer J control register (TMJC) to 0. This function makes TMJ-2, which usually works as an 8-bit counter, work as a 16- bit counter. When this function is selected, timer counter K (TCK) and timer load register K (TLK) must be accessed as follows: TCK Read: To read TCK, use the word-length MOV instruction.
Page 293: Section 14 Timer L
Section 14 Timer L 14.1 Overview Timer A is an 8-bit up/down counter using the control pulses or the CFG division signals as the clock source. 14.1.1 Features Features of timer L are as follows: • Two types of internal clocks (φ/128 and φ/64), DVCFG2 (CFG division signal 2), PB and REC-CTL (control pulses) are available for your selection.
Page 294: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of timer L. INTERNAL CLOCK φ/128 φ/64 Read DVCFG2 OVF/UDF PB and REC-CTL Reloading Match clear Comparator Interrupting circuit Write [Legend] DVCFG2 : Division signal 2 of the CFG Interrupt request PB and REC-CTL : Control pluses necessary when making reproduction and storage LMR : Timer L mode register...
Page 295: Register Configuration
14.1.3 Register Configuration Table 14.1 shows the register configuration of timer L. The linear time counter (LTC) and the reload compare patch register (RCR) are being allocated to the same address. Reading or writing determines the accessing register. Table 14.1 Register Configuration Name Abbrev.
Page 296: Register Descriptions
14.2 Register Descriptions 14.2.1 Timer L Mode Register (LMR) Bit : LMIF LMIE LMR3 LMR2 LMR1 LMR0 — — Initial value : — — R/W : R /(W)* Note: * Only 0 can be written to clear the flag. The timer L mode register A (LMR) is an 8-bit read/write register which works to control the interrupts, to select between up-counting and down-counting and to select the clock source.
Page 297 1. When Controlled to the Up-Counting Function  When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00 before starting counting up. When the LTC value and the RCR value match, the LTC will be cleared to H'00.
Page 298: Linear Time Counter (Ltc)
14.2.2 Linear Time Counter (LTC) Bit : LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 Initial value : R/W : The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be selected by the LMR2 to LMR0 bits of the LMR. When reset, the LTC is initialized to H'00.
Page 299: Module Stop Control Register (Mstpcr)
14.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP12 bit is set to 1, timer L stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 300: Operation
14.3 Operation Timer L is an 8-bit up/down counter. The inputting clock for Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the choices of the internal clock (φ/128 and φ/64), DVCDG2, PB and REC-CTL. Timer L is provided with three different types of operation modes, namely, the compare match clear mode when controlled to the up-counting function, the auto reloading mode when controlled to the down-counting function and the interval timer mode.
Page 301 φ PB-CTL Count-up signal Compare match clear signal H' 00 Interrupt request Figure 14.3 Compare Match Clearing Timing Chart (In case the rising edge of the PB-CTL is selected) Rev. 1.0, 02/00, page 287 of 1141...
Page 302: Section 15 Timer R
Section 15 Timer R 15.1 Overview Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and slow tracking function in addition to the reloading function and event counter function. 15.1.1 Features The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units of reloading timers/counters and by combining three units of timers, it can be used for the following applications: •...
Page 303 Figure 15.1 Block Diagram of Timer R Rev. 1.0, 02/00, page 290 of 1141...
Page 304: Pin Configuration
15.1.3 Pin Configuration Table 15.1 shows the pin configuration of timer R. Table 15.1 Pin Configuration Name Abbrev. Function ,546 Input capture inputting pin Input Input capture inputting for the Timer R 15.1.4 Register Configuration Table 15.2 shows the register configuration of timer R. Table 15.2 Register Configuration Name Abbrev.
Page 305: Register Descriptions
15.2 Register Descriptions 15.2.1 Timer R Mode Register 1 (TMRM1) Bit : CLR2 AC/BR RLCK PS21 PS20 RLD/CAP Initial value : R/W : The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register. When reset, the TMRM1 is initialized to H'00.
Page 306 Bit 5    Using/Not Using the TMRU-2 for Reloading (RLD): This bit is used for selecting if the TMRU-2 reload function is to be turned on or not. Bit 5 Description Not using the TMRU-2 as the reload timer (Initial value) Using the TMRU-2 as the reload timer Bit 4...
Page 307: Timer R Mode Register 2 (Tmrm2)
Bit 0    Capture Signals of the TMRU-1 (CPS): In combination with the LAT bit (Bit 7) of the TMR2, this bit works to select the capture signals of the TMRU-1. This bit becomes valid when the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set to 1.
Page 308 Bit 7    Capture Signals of the TMRU-2 (LAT): In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture signals of the TMRU-2. TMRM2 TMRM1 Bit 7 Bit 0 Description Captures when the TMRU-3 underflows (Initial value) Captures at the rising edge of the CFG...
Page 309 Bit 2    Interrupt Causes (CP/SLM): This bit works to select the interrupt causes for the TMRI3. Bit 2 CP/SLM Description Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value) Makes interrupt requests upon ending of the slow tracking mono-multi valid Bit 1...
Page 310: Timer R Control/Status Register (Tmrcs)
15.2.3 Timer R Control/Status Register (TMRCS) Bit : — — TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 Initial value : — — R/(W)* R/(W)* R/(W)* R/W : Note: * Only 0 can be written to clear the flag. The timer R control/status register (TMRCS) works to control the interrupts of timer R. The TMRCS is an 8-bit read/write register.
Page 311 Bit 5    Enabling the TMRI1 Interrupt (TMRI1E): This bit works to permit/prohibit occurrence of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of the TMRU-1. Bit 5 TMRI1E Description Prohibits occurrences of TMRI1 interrupts (Initial value)
Page 312: Timer R Capture Register 1 (Tmrcp1)
Bit 2    TMRI1 Interrupt Requesting Flag (TMRI1): This is the TMRI1 interrupt requesting flag. It indicates occurrences of the TMRU-1 underflow signals. Bit 2 TMRI1 Description [Clearing conditions] (Initial value) When 0 is written after reading 1. [Setting conditions] When the TMRU-1 underflows.
Page 313: Timer R Capture Register 2 (Tmrcp2)
15.2.5 Timer R Capture Register 2 (TMRCP2) Bit : TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : R/W : The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter readings are captured by the TMRCP2.
Page 314: Timer R Load Register 2 (Tmrl2)
15.2.7 Timer R Load Register 2 (TMRL2) Bit : TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 Initial value : R/W : The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load value of the TMRU-2.
Page 315: Module Stop Control Register (Mstpcr)
15.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP11 bit is set to 1, timer R stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 316: Operation
15.3 Operation 15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1 TMRU-1 is a reload timer counter equipped with capturing function. It consists of an 8-bit down- counter, a reloading register and a capture register. The clock source can be selected from among the leading edge of the CFG signals and three types of dividing clocks.
Page 317: Reload Timer Counter Equipped With Capturing Function Tmru-2
15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 TMRU-2 is a reload timer counter equipped with capturing function. It consists of an 8-bit down- counter, a reloading register and a capture register. The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three types of dividing clocks.
Page 318: Mode Identification
searches. These DVCTL signals can also be used for phase controls of the capstan motor. Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the edges of the DVCTL to provide the slow tracking mono-multi function. 15.3.4 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing...
Page 319: Slow Tracking Mono-Multi Function
underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be cleared by the CFG. • When the acceleration has been finished (when the CFG signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), an interrupt request will be issued because of the CFG.
Page 320 Compensation for vertical vibrations (Supplementary V-pulse) FG acceleration detection Accelerating the Hi-Z capstan motor Acceleration process DVCTL↑ Interrupt Slow tracking mono-multi Slow tracking delay FG stopping detection Reloading Reverse Braking the rotation capstan motor Forward rotation Braking process Braking the Servo drum motor Compensation for...
Page 321: Interrupt Cause
15.4 Interrupt Cause In timer R, bits TMRI1 to TMRI3 of the timer R control/status register cause interrupts. The following are descriptions of the interrupts. 1. Interrupts caused by the underflowing of the TMRU-1 (TMRI1) These interrupts will constitute the timing for reloading with the TMRU-1. 2.
Page 322: Settings For Respective Functions
15.5 Settings for Respective Functions 15.5.1 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the timer R should be used. Timer R will be initialized to this mode identification status after a reset.
Page 323: Reeling Controls
15.5.2 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the ,546 pin, reeling controls, etc. can be effected. Settings •...
Page 324: Acceleration And Braking Processes Of The Capstan Motor
Settings • Setting the timer R mode register 2 (TMRM2)  PS31 and PS30 (bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-3.  CP/SLM bit (bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3 interrupt request.
Page 325  PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-2. • Setting the timer R load register 2 (TMRL2)  Set the count reading for the duration until the braking process finishes. When the count is n, the set value should be (n - 1).
Page 326: Section 16 Timer X1
Section 16 Timer X1 16.1 Overview Timer X1 is capable of outputting two different types of independent waveforms using a 16-bit free running counter (FRC) as the basic means and it is also applicable to measurements of the durations of input pulses and the cycles external clocks. 16.1.1 Features Timer X1 has the following features:...
Page 327: Block Diagram
16.1.2 Block Diagram Figure 16.1 shows a block diagram of the Timer X1. FTIA* ICRA (HSW) FTIB* (VD) ICRB Input FTIC* capture (DVCTL) control ICRC FTID* (NHSW) ICRD TCRX OCRB Comparison circuit (DVCFG) φ / 4 Comparison circuit φ / 16 φ...
Page 328: Pin Configuration
16.1.3 Pin Configuration Table 16.1 shows the pin configuration of timer X1. Table 16.1 Pin Configuration Name Abbrev. Function Output comparing A output-pin FTOA Output Output pin for the output comparing A Output comparing B output-pin FTOB Output Output pin for the output comparing B Input capture A input-pin FTIA Input...
Page 329: Register Configuration
16.1.4 Register Configuration Table 16.2 shows the register configuration of timer X1. Table 16.2 Register Configuration Name Abbrev. Initial Value Address Timer interrupt enabling register TIER H'00 H'D100 Timer control/status register X TCSRX R/ (W) H'00 H'D101 Free running counter H FRCH H'00 H'D102...
Page 330: Register Descriptions
16.2 Register Descriptions 16.2.1 Free Running Counter (FRC) Free running counter H (FRCH) Free running counter L (FRCL) Bit : Initial value : R/W : FRCH FRCL The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external clock.
Page 331: Output Comparing Registers A And B (Ocra And Ocrb)
16.2.2 Output Comparing Registers A and B (OCRA and OCRB) Output comparing register AH and BH (OCRAH and OCRBH) Output comparing register AL and BL (OCRAL and OCRBL) OCRA, OCRB Bit : Initial value : R/W : OCRAH, OCRBH OCRAL, OCRBL The OCR consists of twin 16-bit read/write registers (OCRA and OCRB).
Page 332: Input Capture Registers A Through D (Icra Through Icrd)
16.2.3 Input Capture Registers A Through D (ICRA Through ICRD) Input capture register AH to DH (ICRAH to ICRDH) Input capture register AL to DL (ICRAL to ICRDL) ICRA, ICRB, ICRC, ICRD Bit : Initial value : R/W : ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL The ICR consists of four 16-bit read-only registers (ICRA through ICRD).
Page 333 IEDGA BUFEA IEDGC Edge detection and FTIA capture signal generating circuit. ICRC ICRA Figure 16.2 Buffer Operation (Example) Table 16.3 Input Signal Edge Selection when Making Buffer Operation IEDGA IEDGC Selection of the Input Signal Edge Captures at the falling edge of the input capture input A (Initial value) Captures at both rising and falling edges of the input capture input A Captures at the rising edge of the input capture input A Reading can be made from the ICR through the CPU at 8-bit or 16-bit.
Page 334: Timer Interrupt Enabling Register (Tier)
16.2.4 Timer Interrupt Enabling Register (TIER) Bit : ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA Initial value : R/W : The TIER is an 8-bit read/write register that controls permission/prohibition of interrupt requests. The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
Page 335 Bit 4    Enabling the Input Capture Interrupt D (ICIDE): This bit works to permit/prohibit interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1. Bit 4 ICIDE Description Prohibits interrupt requests (ICID) by the ICFD (Initial value) Permits interrupt requests (ICID) by the ICFD Bit 3...
Page 336 Bit 0    Selecting the Input Capture A Signals (ICSA): This bit works to select the input capture A signals. Bit 0 ICSA Description Selects the FTIA pin for inputting of the input capture A signals (Initial value) Selects the HSW for inputting of the input capture A signals Rev.
Page 337: Timer Control/Status Register X (Tcsrx)
16.2.5 Timer Control/Status Register X (TCSRX) Bit : ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag for Bits 7 to 1. The TCSRX is an 8-bit register which works to select counter clearing timing and to control respective interrupt requesting signals.
Page 338 Bit 6    Input Capture Flag B (ICFB): This status flag indicates the fact that the value of the FRC has been transferred to the ICRB by the input capture signals. When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value has been transferred to the ICRB by the input capture signals and that the ICRB value before being updated has been transferred to the ICRC.
Page 339 Bit 4    Input Capture Flag D (ICFD): This status flag indicates the fact that the value of the FRC has been transferred to the ICRD by the input capture signals. When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the ICFD will be set out, data transference to the ICRD will not be performed.
Page 340 Bit 2    Output Comparing Flag B (OCFB): This status flag indicates the fact that the FRC and the OCRB have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware.
Page 341: Timer Control Register X (Tcrx)
16.2.6 Timer Control Register X (TCRX) Bit : IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value : R/W : The TCRX is an 8-bit read/write register that selects the input capture signal edge, designates the buffer operation, and selects the inputting clock for the FRC. The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
Page 342 Bit 4    Input Capture Signal Edge Selection D (IEDGD): This bit works to select the rising edge or falling edge of the input capture signal D (FTID). Bit 4 IEDGD Description Captures the falling edge of the input capture signal D (Initial value) Captures the rising edge of the input capture signal D Bit 3...
Page 343: Timer Output Comparing Control Register (Tocr)
16.2.7 Timer Output Comparing Control Register (TOCR) Bit : ICSB ICSC ICSD OSRS OLVLA OLVLB Initial value : R/W : The TOCR is an 8-bit read/write register that select input capture signals and output comparing output level, permits output comparing outputs, and controls switching over of the access of the OCRA and OCRB.
Page 344 Bit 4    Selecting the Output Comparing Register (OCRS): The addresses of the OCRA and OCRB are the same. The OCRS works to control which register to choose when reading/writing this address. The choice will not influence the operation of the OCRA and OCRB. Bit 4 OCRS Description...
Page 345: Module Stop Control Register (Mstpcr)
Bit 0    Output Level B (OLVLB): This bit works to select the output level to output through the FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB). Bit 0 OLVLB Description Low level (Initial value)
Page 346: Operation
16.3 Operation 16.3.1 Operation of Timer X1 • Output Comparing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX.
Page 347: Counting Timing Of The Frc
16.3.2 Counting Timing of the FRC The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the inputting clock can be selected from among three different types of clocks (φ/4, φ/16 and φ/64) and the DVCFG.
Page 348: Output Comparing Signal Outputting Timing
16.3.3 Output Comparing Signal Outputting Timing When a comparing match occurs, the output level having been set by the OLVL of the TOCR is output through the output comparing signal outputting pins (FTOA and FTOB). Figure 16.5 shows the timing chart for the output comparing signal outputting A. φ...
Page 349: Input Capture Signal Inputting Timing
16.3.5 Input Capture Signal Inputting Timing • Input Capture Signal Inputting Timing As for the input capture signal inputting, rising or falling edge is selected by settings of the IEDGA through IEDGD bits of the TCRX. Figure 16.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD = φ...
Page 350: Input Capture Flag (Icfa Through Icfd) Setting Up Timing
Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up corresponding to the designated edge change of respective input capture signals. For example, when using the ICRC as the buffer register for the ICRA, when an edge change having been designated by the IEDGC bit is detected with the input capture signals C and if the ICIEC bit is duly set, an interrupt request will be issued.
Page 351: Output Comparing Flag (Ocfa And Ocfb) Setting Up Timing
16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing The OCFA and OCFB are being set to 1 by the comparing match signal being output when the values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last state of the value match (the timing of the FRC's updating the matching count reading).
Page 352: Operation Mode Of Timer X1
16.4 Operation Mode of Timer X1 Table 16.4 indicated below shows the operation mode of Timer X1. Table 16.4 Operation Mode of Timer X1 Operation Module Mode Reset Active Sleep Watch Subactive Standby Subsleep Stop Reset Functions Functions Reset Reset Reset Reset Reset...
Page 353: Interrupt Causes
16.5 Interrupt Causes Total seven interrupt causes exist with Timer X1, namely, ICIA through ICID, OCIA, OCIB and FOVI. Table 16.5 lists the contents of interrupt causes. Interrupt requests can be permitted or prohibited by setting interrupt enabling bits of the TIER. Also, independent vector addresses are allocated to respective interrupt causes.
Page 354: Exemplary Uses Of Timer X1
16.6 Exemplary Uses of Timer X1 Figure 16.12 shows an example of outputting at optional phase difference of the pulses of the 50% duty. For this setting, follow the procedures listed below. 1. Set the CCLRA bit of the TCSRX to 1. 2.
Page 355: Precautions When Using Timer X1
16.7 Precautions when Using Timer X1 Pay great attention to the fact that the following competitions and operations occur during operation of timer X1. 16.7.1 Competition between Writing and Clearing with the FRC When a counter clearing signal is issued under the T2 state where the FRC is under the writing cycle, writing into the FRC will not be effected and the priority will be given to clearing of the FRC.
Page 356: Competition Between Writing And Counting Up With The Frc
16.7.2 Competition between Writing and Counting Up with the FRC When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the counting up will not be effected and the priority will be given to count writing. Figure 16.14 shows the timing chart.
Page 357: Competition Between Writing And Comparing Match With The Ocr
16.7.3 Competition between Writing and Comparing Match with the OCR When a comparing match occurs under the T2 state where the OCRA and OCRB are under the writing cycle, the priority will be given to writing of the OCR and the comparing match signal will be prohibited.
Page 358: Changing Over The Internal Clocks And Counter Operations
16.7.4 Changing Over the Internal Clocks and Counter Operations Depending on the timing of changing over the internal clocks, the FRC may count up. Table 16.6 shows the relations between the timing of changing over the internal clocks (Re-writing of the CKS1 and CKS0) and the FRC operations.
Page 359 Rewriting Timing for the CKS1 and CKS0 FRC Operation High → low level Clock before changeover the changeover Clock after the changeover Count clock Rewriting of the CKS1 and CKS0 High → high level Clock before changeover the changeover Clock after the changeover Count clock...
Page 360: Section 17 Watchdog Timer (Wdt)
Section 17 Watchdog Timer (WDT) 17.1 Overview This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal.
Page 361: Block Diagram
17.1.2 Block Diagram Figure 17.1 shows block diagram of WDT. φ / 2 φ / 64 WOVI φ / 128 (Interrupt request signal) Interrupt φ / 512 Clock control Overflow Clock Internal NMI φ / 2048 select • interrupt request signal φ...
Page 362: Register Configuration
17.1.3 Register Configuration The WDT has two registers, as described in table 17.1. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 17.1 WDT Registers Address Name Abbrev. Initial Value Write Read Watchdog timer WTCSR R/ (W) H'00 H'FFBC H'FFBC...
Page 363: Register Descriptions
17.2 Register Descriptions 17.2.1 Watchdog Timer Counter (WTCNT) Bit : Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.
Page 364 Bit 7    Overflow Flag (OVF): A status flag that indicates that WTCNT has overflowed from H'FF to H'00. Bit 7 Description [Clearing conditions] (Initial value) 1. Write 0 in the TME bit 2. Read WTCSR when OVF = 1, then write 0 in OVF [Setting condition] When WTCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is...
Page 365 Bit 3    Reset or NMI (RST/10, 10,): Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in watchdog timer mode. Bit 3 RST/10, Description An NMI interrupt request is generated (Initial value) An internal reset request is generated Bits 2 to 0...
Page 366: System Control Register (Syscr)
17.2.3 System Control Register (SYSCR) Bit : — — INTM1 INTM0 XRST — — — Initial value : — — — — — R/W : Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Page 367: Notes On Register Access
17.2.4 Notes on Register Access The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. • Writing to WTCNT and WTCSR These registers must be written to by a word transfer instruction.
Page 368: Operation
17.3 Operation 17.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/,7 and TME bits in WTCSR to 1. Software must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. This ensures that WTCNT does not overflow while the system is operating normally.
Page 369: Interval Timer Operation
17.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/,7 bit in WTCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 17.4.
Page 370: Timing Of Setting Of Overflow Flag (Ovf)
17.3.3 Timing of Setting of Overflow Flag (OVF) The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 17.5. If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF bit in WTCSR is set to 1 and at the same time an NMI interrupt is requested.
Page 371: Interrupts
17.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in WTCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request.
Page 372: Changing Value Of Cks2 To Cks0
17.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.
Page 373: Section 18 8-Bit Pwm
Section 18 8-Bit PWM 18.1 Overview The 8-bit PWM incorporates 4 channels of the duty control method. Its outputs can be used to control a reel motor or loading motor. 18.1.1 Features • Conversion period: 256-state • Duty control method 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the 8-bit PWM (1 channel).
Page 374: Pin Configuration
18.1.3 Pin Configuration Table 18.1 shows the 8-bit PWM pin configuration. Table 18.1 Pin Configuration Name Abbrev. Function 8-bit PWM square-wave output pin 0 PWM0 Output 8-bit PWM square-wave output 0 8-bit PWM square-wave output pin 1 PWM1 Output 8-bit PWM square-wave output 1 8-bit PWM square-wave output pin 2 PWM2 Output...
Page 375: Register Descriptions
18.2 Register Descriptions 18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) PWR0 Bit : PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00 Initial value : R/W : PWR1 Bit : PW17 PW16 PW15 PW14 PW13 PW12 PW11...
Page 376: 8-Bit Pwm Control Register (Pw8Cr)
18.2.2 8-bit PWM Control Register (PW8CR) Bit : — — — — PWC3 PWC2 PWC1 PWC0 Initial value : — — — — R/W : The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls PWM functions. PW8CR is initialized to H'00 by a reset. Bits 7 to 4...
Page 377: Port Mode Register 3 (Pmr3)
18.2.3 Port Mode Register 3 (PMR3) Bit : PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Initial value : R/W : The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching is specified for each bit. The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset.
Page 378: Module Stop Control Register (Mstpcr)
18.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle and transits to the module stop mode.
Page 379: 8-Bit Pwm Operation
18.3 8-Bit PWM Operation The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width determined by the data registers (PWR). The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter. Figure 18.2 shows the output waveform example of 8-bit PWM.
Page 380: Section 19 12-Bit Pwm
Section 19 12-Bit PWM 19.1 Overview The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the drum and capstan motor controller. 19.1.1 Features Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the pulse-pitch control method (periodically overriding part of the output).
Page 381: Block Diagram
19.1.2 Block Diagram Figure 19.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from the contents of a data register. Low-frequency components are reduced because the two quantizing pulses have different frequencies.
Page 382: Pin Configuration
19.1.3 Pin Configuration Table 19.1 shows the 12-bit PWM pin configuration. Table 19.1 Pin Configuration Name Abbrev. Function Capstan mix CAPPWM Output 12-bit PWM square-wave output Drum mix DRMPWM 19.1.4 Register Configuration Table 19.2 shows the 12-bit PWM register configuration. Table 19.2 12-Bit PWM Registers Name Abbrev.
Page 383: Register Descriptions
19.2 Register Descriptions 19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR) CPWCR Bit : CPOL CHiZ CH/L CSF/DF CCK2 CCK1 CCK0 Initial value : R/W : DPWCR Bit : DPOL DHiZ DH/L DSF/DF DCK2 DCK1 DCK0 Initial value : R/W : CPWCR is the PWM output control register for the capstan motor.
Page 384 Bits 5 and 4    PWM Pin Output (HiZ, H/L): When bit DC is set to 1, the 12-bit PWM output pins (CAPPWM, DRMPWM) output a value determined by the HiZ and H/L bits. The output is not affected by bit POL. In power-down modes, the 12-bit PWM circuit and pin statuses are retained.
Page 385 Bits 2 to 0    Carrier Frequency Select (CK2 to CK0): Selects the carrier frequency of the PWM modulated signal. Do not set them to 111. Bit 2 Bit 1 Bit 0 Description φ2 φ4 φ8 (Initial value) φ16 φ32 φ64...
Page 386: 12-Bit Pwm Data Registers (Dpwdr, Cpwdr)
19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR) CPWDR Bit : — — — — CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 Initial value : R/W : — — — — DPWDR Bit : — — —...
Page 387: Operation
19.3 Operation 19.3.1 Output Waveform The PWM signal generator combines the error data with the output from an internal pulse generator to produce a pulse-width modulated signal. When Vcc/2 is set as the reference value, the following conditions apply: 1. When the motor is running at the correct speed and phase, the PWM signal is output with a 50% duty cycle.
Page 388 Figure 19.2 Sample Waveform Output by 12-Bit PWM (4 Bits) Rev. 1.0, 02/00, page 377 of 1141...
Page 389: Section 20 14-Bit Pwm
Section 20 14-Bit PWM 20.1 Overview The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. 20.1.1 Features Features of the 14-bit PWM are given below: • Choice of two conversion periods A conversion period of 32768/φ...
Page 390: Block Diagram
20.1.2 Block Diagram Figure 20.1 shows a block diagram of the 14-bit PWM. PWCR PWDRL PWDRU φ/4 PWM waveform PWM14 φ/2 generator [Legend] PWCR : PWM control register PWDRL : PWM data register L PWDRU : PWM data register U PWM14 : PWM14 output pin Figure 20.1 Block Diagram of 14-Bit PWM...
Page 391: Register Configuration
20.1.4 Register Configuration Table 20.2 shows the 14-bit PWM register configuration. Table 20.2 14-Bit PWM Registers Name Abbrev. Size Initial Value Address* PWM control register PWCR Byte H'FE H'D122 PWM data register U PWDRU Byte H'00 H'D121 PWM data register L PWDRL Byte H'00...
Page 392: Register Descriptions
20.2 Register Descriptions 20.2.1 PWM Control Register (PWCR) Bit : — — — — — — — PWCR0 Initial value : — — — — — — — R/W : The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM functions.
Page 393: Pwm Data Registers U And L (Pwdru, Pwdrl)
20.2.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU Bit : — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Initial value : R/W : — — PWDRL Bit : PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value : R/W : PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN waveform cycle.
Page 394: Module Stop Control Register (Mstpcr)
20.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that control the module stop mode functions.
Page 395: 14-Bit Pwm Operation
20.3 14-Bit PWM Operation When using the 14-bit PWM, set the registers in this sequence: 1. Set bit PWM40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for PWM output. 2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32768/φ...
Page 396: Section 21 Prescalar Unit
Section 21 Prescalar Unit 21.1 Overview The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses φ as a clock source and a 5-bit counter that uses φW as a clock source. 21.1.1 Features • Prescalar S (PSS) Generates frequency division clocks that are input to peripheral functions.
Page 397: Block Diagram
21.1.2 Block Diagram Figure 21.1 shows a block diagram of the prescalar unit. PWM3 PWM2 PWM1 Stable oscillation PWM0 wait time count output 6 bits 8 bits Prescalar S φ/131072 to φ/2 φ 18-bit free running counter (FRC) 8 bits φ/4 φ/8 φ/16...
Page 398: Pin Configuration
21.1.3 Pin Configuration Table 21.1 shows the pin configuration of the prescalar unit. Table 21.1 Pin Configuration Name Abbrev. Function ,& Input capture input Input Prescalar unit input capture input pin Frequency division clock TMOW Output Prescalar unit frequency division clock output output pin 21.1.4...
Page 399: Registers
21.2 Registers 21.2.1 Input Capture Register 1 (ICR1) Bit : ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 Initial value : R/W : Input capture register 1 (ICR1) captures 8-bit data of 2 to 2 of the FRC according to the edge of the ,&...
Page 400 Bit 6    Input Capture Interrupt Enable (ICIE): When ICIF was set to 1 by the input capture according to the edge of the ,& pin, ICIE enables and disables the generation of an input capture interrupt. Bit 6 ICIE Description Disables the generation of an input capture interrupt...
Page 401 Bits 2 to 0    Frequency Division Clock Output Select (DCS2 to DCS0): DCS2 to DCS0 select eight types of frequency division clocks that are output from the TMOW pin. Bit 2 Bit 1 Bit 0 DCS2 DCS1 DCS0 Description Outputs PSS, φ/32...
Page 402: Port Mode Register 1 (Pmr1)
21.2.3 Port Mode Register 1 (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register.
Page 403: Noise Cancel Circuit
21.3 Noise Cancel Circuit The ,& pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such as remote control receiving. The noise cancel circuit samples the input values of the ,& pin twice at an interval of 256 states.
Page 404: Prescalar W (Psw)
21.4.2 Prescalar W (PSW) PSW is a counter that uses the subclock as an input clock. The PSW also generates the input clock of the timer A. In this case, the timer A functions as a clock time base. When reset, the PSW is initialized to H'00, and starts increment after reset has been released. Even if the mode has been shifted to the standby mode *, watch mode *, subactive mode *, and subsleep mode *, the PSW continues the operation as long as the clocks are supplied by the X1 and X2 pins.
Page 405: 8-Bit Pwm
21.4.4 8-bit PWM This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It counts the cycle and the duty cycle at 2 to 2 of the FRC. It can be used for controlling reel motors and loading motors.
Page 406: Section 22 Serial Communication Interface 1 (Sci1)
Section 22 Serial Communication Interface 1 (SCI1) 22.1 Overview The serial communication interface (SCI) can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 22.1.1 Features SCI1 features are listed below. •...
Page 407 • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...
Page 408: Block Diagram
22.1.2 Block Diagram Figure 22.1 shows a block diagram of the SCI. Module data bus RDR1 TDR1 SCMR1 BRR1 SSR1 φ SCR1 Baud rate φ/4 RSR1 TSR1 generator SMR1 φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock SCK1 [Legend] RSR1...
Page 409: Pin Configuration
22.1.3 Pin Configuration Table 22.1 shows the serial pins used by the SCI. Table 22.1 SCI Pins Channel Pin Name Symbol Function Serial clock pin 1 SCK1 SCI1 clock input/output Receive data pin 1 Input SCI1 receive data input Transmit data pin 1 Output SCI1 transmit data output 22.1.4...
Page 410: Register Descriptions
22.2 Register Descriptions 22.2.1 Receive Shift Register 1 (RSR1) Bit : R/W : — — — — — — — — RSR1 is a register used to receive serial data. The SCI sets serial data input from the SI1 pin in RSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 411: Transmit Shift Register 1 (Tsr1)
22.2.3 Transmit Shift Register 1 (TSR1) Bit : R/W : — — — — — — — — TSR1 is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR1 to TSR1, then sends the data to the SO1 pin starting with the LSB (bit 0).
Page 412: Serial Mode Register 1 (Smr1)
22.2.5 Serial Mode Register 1 (SMR1) Bit : STOP CKS1 CKS0 Initial value : R/W : SMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR1 can be read or written to by the CPU at all times. SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
Page 413 Bit 5    Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting.
Page 414 Bit 3    Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...
Page 415: Serial Control Register 1 (Scr1)
Bits 1 and 0    Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 22.2.8, Bit Rate Register 1.
Page 416 Bit 6    Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR1 to RDR1 and the RDRF flag in SSR1 is set to 1. Bit 6 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request...
Page 417 Bit 3    Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR1 set to 1. The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
Page 418 Bits 1 and 0    Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
Page 419: Serial Status Register 1 (Ssr1)
22.2.7 Serial Status Register 1 (SSR1) Bit : TDRE RDRF ORER TEND MPBT Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
Page 420 Bit 5    Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description [Clearing conditions] (Initial value) When 0 is written in ORER after reading ORER = 1 [Setting conditions] When the next serial reception is completed while RDRF = 1 Notes: 1.
Page 421 Bit 3    Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 4 Description [Clearing conditions] (Initial value) When 0 is written in PER after reading PER = 1 [Setting conditions] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/( bit in SMR1...
Page 422: Bit Rate Register 1 (Brr1)
Bit 0    Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode.
Page 423 Table 22.3 BRR1 Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ φ φ φ (MHz) 2.097152 2.4576 Error Error Error Error Bit Rate (bits/s) −0.04 −0.26 0.03 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 −0.70...
Page 424 Operating Frequency φ φ φ φ (MHz) 6.144 7.3728 Error Error Error Error Bit Rate (bits/s) −0.44 −0.07 0.08 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16 0.00 0.00 0.16 2400 0.16 0.00 0.00 0.16 4800...
Page 425 Table 22.4 BRR1 Settings for Various Bit Rates (Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Bit Rate (bits/s)         2.5 k 10 k 25 k 50 k 100 k 250 k 500 k 2.5 M Note: As far as possible, the setting should be made so that the error is no more than 1%.
Page 426 The BRR1 setting is found from the following equations. • Asynchronous mode: φ 6 − 1 × 10 64 × 2 × B 2n−1 • Synchronous mode: φ 6 − 1 × 10 8 × 2 × B 2n−1 Where Bit rate (bits/s) BRR1 setting for baud rate generator (0 ≤...
Page 427 Table 22.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ φ φ φ (MHz) Maximum Bit Rate (bits/s) 62500 2.097152 65536 2.4576 76800 93750 3.6864 115200 125000 4.9152 153600 156250 187500 6.144 192000 7.3728 230400 250000 9.8304 307200 312500 Rev.
Page 428 Table 22.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500...
Page 429: Serial Interface Mode Register 1 (Scmr1)
22.2.9 Serial Interface Mode Register 1 (SCMR1) Bit : — — — — SDIR SINV — SMIF Initial value : R/W : — — — — — SCMR1 is an 8-bit readable/writable register used to select SCI functions. SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
Page 430: Module Stop Control Register (Mstpcr)
22.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 431: Operation
22.3 Operation 22.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR1 as shown in table 22.8.
Page 432 Table 22.8 SMR1 Settings and Serial Transfer Format Selection SMR1 Settings SCI Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multiproc- Parity Stop Bit C/$ $ $ $ STOP Mode Length essor Bit Length Asynchro- 8-bit 1 bit nous mode...
Page 433: Operation In Asynchronous Mode
22.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by- character basis.
Page 434 • Data Transfer Format Table 22.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR1. Table 22.10 Serial Transfer Formats (Asynchronous Mode) SMR1 Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP...
Page 435 • Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/$ bit in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI clock source selection, see table 22.9.
Page 436 • Data Transfer Operations  SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 437  Serial Data Transmission (Asynchronous Mode) Figure 22.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. SCI initialization: Initialization The SO1 pin is automatically designated as the transmit data output pin. Start transmission SCI status check and transmit data write: Read SSR and check that the TDRE flag is...
Page 438 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR1. 2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts transmission.
Page 439 Figure 22.6 shows an example of the operation for transmission in asynchronous mode. Data Data Start Parity Stop Parity Stop Start Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR1 and TXI interrupt request TEI interrupt request request TDRE flag cleared to 0 generated...
Page 440  Serial Data Reception (Asynchronous Mode) Figures 22.7 and 22.8 show sample flowcharts for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The SI1 pin is automatically designated as the receive data input pin. Start reception Receive error handling and break [2][3]...
Page 441 Error handling ORER=1 Overrun error handling FER=1 Break? Framing error handling Clear RE bit in SCR1 to 0 PER=1 Parity error handling Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 22.8 Sample Serial Reception Data Flowchart (2) Rev.
Page 442 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in RSR1 in LSB-to-MSB order. 3.
Page 443: Multiprocessor Communication Function
Figure 22.9 shows an example of the operation for reception in asynchronous mode. Data Data Start Parity Stop Parity Stop Start Idle state (mark state) RDRF RXI interrupt RDR1 data read ERI interrupt request request and RDRF flag generated by framing generation cleared to 0 in error...
Page 444 1. Data Transfer Format There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 22.10. 2. Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving Receiving Receiving...
Page 445 SCI initialization: Initialization The SO2 pin is automatically designated as the transmit data output pin. Start transmission SCI status check and transmit data write: Read SSR and check that the TDRE flag is Read TDRE flag in SSR1 set to 1, then write transmit data to TDR1. Set the MPBT bit in SSR1 to 0 or 1.
Page 446 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR1. 2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts transmission.
Page 447 Figure 22.12 shows an example of SCI operation for transmission using a multiprocessor format. Multi- Multi- Data Data processor Start processor Stop Start Stop bit 1 Idle state (mark state) TDRE TEND Data written to TDR1 and TXI interrupt request TXI interrupt TEI interrupt TDRE flag cleared to 0...
Page 448 Initialization SCI initialization: The SI1 pin is automatically designated as the receive data input pin. Start reception ID reception cycle: Set the MPIE bit in SCR1 to 1. Set MPIE bit in SCR1 to 1 SCI status check, ID reception and Read ORER and FER flags in SSR1 comparison: Read SSR and check that the RDRF flag is...
Page 449 Error handling ORER=1 Overrun error handling FER=1 Break? Framing error handling Clear RE bit in SCR1 to 0 Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 22.14 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.0, 02/00, page 440 of 1141...
Page 450 Figure 22.15 shows an example of SCI operation for multiprocessor format reception. Data (ID1) Data (Data 1) Start Stop Start Stop Idle state (mark state) MPIE RDRF RDR1 value MPIE=0 RXI interrupt RDR1 data read If not this station's RXI interrupt request request (multi- is not generated, and and RDRF flag...
Page 451: Operation In Synchronous Mode
22.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
Page 452 • Data Transfer Operations  SCI Initialization (Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 453  Serial Data Transmission (Synchronous Mode) Figure 22.18 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. SCI initialization: Initialization The SO2 pin is automatically designated as the transmit data output pin. Start transmission SCI status check and transmit data write: Read SSR1 and check that the TDRE flag...
Page 454 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR1. 2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts transmission.
Page 455  Serial Data Reception (Synchronous Mode) Figure 22.20 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
Page 456 SCI initialization: Initialization The SI1 pin is automatically designated as the receive data input pin. Start reception Receive error handling: [2][3] IF a receive error occurs, read the ORER flag in SSR1, and after performing the Read ORER flag in SSR1 appropriate error handling, clear the ORER flag to 0.
Page 457 In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in RSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR1 to RDR1.
Page 458  Simultaneous Serial Data Transmission and Reception (Synchronous Mode) Figure 22.22 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. SCI initialization: Initialization The SO2 pin is designated as the transmit data output pin, and the SI1 pin is Start transfer designated as the receive data input pin,...
Page 459: Sci Interrupts
22.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 22.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR1. Each kind of interrupt request is sent to the interrupt controller independently.
Page 460: Usage Notes
22.5 Usage Notes The following points should be noted when using the SCI. • Relation between Writes to TDR1 and the TDRE Flag The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred from TDR1 to TSR1.
Page 461 • Break Detection and Processing When framing error (FER) detection is performed, a break can be detected by reading the SI1 pin value directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
Page 462 16 clocks 8 clocks 15 0 15 0 Internal basic clock Receive data Start bit Synchronization sampling timing Data sampling timing Figure 22.23 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. | D –...
Page 463 • Operation in Case of Mode Transition  Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, standby mode, watch mode, subactive mode, or subsleep mode transition. TSR1, TDR1, and SSR1 are reset. The output pin states in module stop mode, standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared.
Page 464 <Transmission> [1] Data being transmitted is interrupted. All data transmitted? After exiting software standby mode, etc., normal CPU transmis- sion is possible by setting TE to 1, reading SSR1, writing TDR1, and Read TEND flag in SSR1 clearing TDRE to 0. [2] If TIE and TEIE are set to 1, clear TEND = 1 them to 0 in the same way.
Page 465 Transition Exit from End of Start of transmission transmission to standby standby TE bit Port input/output SCK1 output pin SO1 output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 22.25 Asynchronous Transmission Using Internal Clock End of Transition...
Page 466 <Reception> Read RDRF flag in SSR1 Receive data being received RDRF= 1 becomes invalid. Read receive data in RDR1 RE= 0 Transition to standby Includes module stop mode, mode, etc. watch mode, subactive mode, and subsleep mode. Exit from standby mode, etc.
Page 467: Section 23 I C Bus Interface (Iic)
Section 23 I C Bus Interface (IIC) 23.1 Overview This LSI incorporates a 2-channel I C bus interface. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 468: Block Diagram
23.1.2 Block Diagram Figure 23.1 shows a block diagram of the I C bus interface. Figure 23.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to input pins depend on the power (Vcc) voltage of this LSI.
Page 469: Pin Configuration
(Master) This chip (Slave 1) (Slave 2) Figure 23.2 I C Bus Interface Connections (Example: This Chip as Master) 23.1.3 Pin Configuration Table 23.1 summarizes the input/output pins used by the I C bus interface. Table 23.1 I C Bus Interface Pins Channel Name Abbrev.* I/O Function...
Page 470: Register Configuration
23.1.4 Register Configuration Table 23.2 summarizes the registers of the I C bus interface. Table 23.2 Register Configuration Channel Name Abbrev. Initial Value Address C bus control register ICCR0 H'01 H'D0E8 C bus status register ICSR0 H'00 H'D0E9  C bus data register ICDR0 H'D0EE* C bus mode register...
Page 471: Register Descriptions
23.2 Register Descriptions 23.2.1 C Bus Data Register (ICDR) Bit : ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value : — — — — — — — — R/W : ICDRR Bit : ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0...
Page 472 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
Page 473 TDRE Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] (Initial value) 1. When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) 2. When a stop condition is detected in the bus line state after a stop condition is issued with the I C bus format or serial format selected 3.
Page 474: Slave Address Register (Sar)
23.2.2 Slave Address Register (SAR) Bit : SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 Initial value : R/W : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 475 Bit 0    Format Select (FS): Used together with the FSX bit in SARX and the SW bit in DDCSWR to select the communication format. • I C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only •...
Page 476: Second Slave Address Register (Sarx)
23.2.3 Second Slave Address Register (SARX) Bit : SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 Initial value : R/W : SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 477: C Bus Mode Register (Icmr)
23.2.4 C Bus Mode Register (ICMR) Bit : WAIT CKS2 CKS1 CKS0 Initial value : R/W : ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count.
Page 478 Bit 6    Wait Insertion Bit (WAIT) Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
Page 479 Bits 5 to 3    Transfer Clock Select (CKS2 to CKS0): These bits, together with the IICX1 bit (for channel 1) or IICX0 bit (for channel 0) in STCR, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bits 5, 6 Bit 5...
Page 480 Bits 2 to 0    Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit.
Page 481: C Bus Control Register (Iccr)
23.2.5 C Bus Control Register (ICCR) Bit : IEIC ACKE BBSY IRIC Initial value : R/(W)* R/W : Note: * Only 0 can be written to clear the flag. ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the I...
Page 482 Bits 5 and 4    Master/Slave Select (MST) and Transmit/Receive Select (TRS): MST selects whether the I C bus interface operates in master mode or slave mode. TRS selects whether the I C bus interface operates in transmit mode or receive mode. In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode.
Page 483 Bit 4 Description Receive mode (Initial value) [Clearing conditions] 1. When 0 is written by software (in cases other than setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3) 3.
Page 484 Bit 2    Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1.
Page 485 Bit 1 IRIC Description Waiting for transfer, or transfer in progress (Initial value) [Clearing condition] When 0 is written in IRIC after reading IRIC = 1 Interrupt requested [Setting conditions] • I C bus format master mode 1. When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) 2.
Page 486 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
Page 487 Table 23.3 Flags and Transfer States BBSY ESTP STOP IRTR AASX AL ACKB State Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match...
Page 488: C Bus Status Register (Icsr)
23.2.6 C Bus Status Register (ICSR) Bit : ESTP STOP IRTR AASX ACKB Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control.
Page 489 Bit 6    Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been detected after completion of frame transfer in I C bus format slave mode. Bit 6 STOP Description No normal stop condition (Initial value) [Clearing condition] 1.
Page 490 Bit 4    Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX.
Page 491 Bit 2    Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Page 492: Serial/Timer Control Register (Stcr)
Bit 0    Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device.
Page 493: Ddc Switch Register (Ddcswr)
23.2.8 DDC Switch Register (DDCSWR) Bit : CLR3 CLR2 CLR1 CLR0 Initial value : R/W : R/(W)* Notes: 1. Only 0 can be written to clear the flag. Always read as 1. DDCSWR is an 8-bit read/write register that controls automatic format switching for IIC channel 0 and IIC internal latch clearing.
Page 494 Bit 5    DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when the format for IIC channel 0 is automatically switched. Bit 5 Description Disables an interrupt at automatic format switching (Initial value) Enables an interrupt at automatic format switching Bit 4...
Page 495 Bit 3 Bit 2 Bit 1 Bit 0 CLR3 CLR2 CLR1 CLR0 Description   This setting must not be used This setting must not be used IIC0 internal latch cleared IIC1 internal latch cleared IIC 0 and IIC1 internal latches cleared ...
Page 496: Module Stop Control Register (Mstpcr)
23.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
Page 497: Operation
23.3 Operation 23.3.1 C Bus Data Format The I C bus interface has serial and I C bus formats. The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 23.3(1) and (2). The first frame following a start condition always consists of 8 bits. Formatless transfer can be selected only for IIC channel 0.
Page 498: Master Transmit Operation
FS = 1 and FSX = 1 DATA DATA Transfer bit count (n = 1 to 8) Transfer frame count (m = 1 or above) Figure 23.4 I C Bus Data Format (Serial Format) DATA DATA Figure 23.5 I C Bus Timing Table 23.4 I C Bus Data Format Symbols Symbol...
Page 499 TDRE internal flag is set to 1 and the IRIC and IRTR flags are also set to 1. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. 3. If bit FS is 0 in SAR or bit FSX is 0 in SARX, the first frame following the start condition contains a 7-bit slave address and indicates the transmit/receive direction.
Page 500 Start condition issuance (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address Data 1 (Slave output) TDRE Interrupt Interrupt request IRIC request generated generated ICDRT Data 1...
Page 501 When continuously transmitting data, 6. Clear IRIC flag to 0 before startup of the 9th transmit clock of the data being transmitted, and then write the next transmit data in ICDR. 7. 1 frame data transmission ends, and upon startup of the 9th transmit clock, IRIC flag in ICCR is set to 1.
Page 502: Master Receive Operation
23.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits the data. The receive procedure and operations in master receive mode are described below. 1.
Page 503 Master transmit Master receive mode mode (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Slave output) Data 1 Data 2 (Master output) RDRF Interrupt Interrupt IRIC request request generated...
Page 504: Slave Receive Operation
23.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The receive procedure and operations in slave receive mode are described below. 1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode.
Page 505 Start condition issurance (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address Data 1 (Slave output) RDRF Interrupt request IRIC generated ICDRS Address + R/W ICDRR...
Page 506 (Master output) (Slave output) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Master output) Data 1 Data 2 (Slave output) RDRF Interrupt Interrupt IRIC request request generated generated ICDRS Data 1 Data 2...
Page 507: Slave Transmit Operation
23.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave transmit mode are described below. 1.
Page 508: Iric Setting Timing And Scl Control
Slave receive mode Slave transmit mode (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Slave output) Data 1 Data 2 (Master output) TDRE Interrupt Interrupt Interrupt IRIC...
Page 509 (a) When WAIT = 0, and FS = 0 or FSX = 0 (I C bus format, no wait) IRIC User Clear Write to ICDR (transmit) or processing IRIC read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC User...
Page 510: Automatic Switching From Formatless Transfer To I
23.3.7 Automatic Switching from Formatless Transfer to I C Bus Format Transfer Setting the SW bit in DDCSWR to 1 selects the IIC0 formatless transfer operation. When an SCL falling edge is detected, the operating mode automatically switches from formatless transfer to I bus format transfer (slave mode).
Page 511: Noise Canceler
23.3.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 23.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 512 Start Test the status of the SCL and SDA lines. Initialize Select master transmit mode. Read BBSY flag in ICCR Generate a start condition. Set transmit data for the first byte (slave BBSY=0? address +R/W) Wait for 1 byte to be transmitted. Set MST=1 and TRS=1 in ICCR Test for acknowledgement by the...
Page 513 Master receive mode Select receive mode. Set TRS=0 in ICCR Set acknowledge data. Clear IRIC flag in ICCR Start receiving. The first read is a dummy Set ACKB=0 in ICSR read. Wait for 1 byte to be received. Last receive? Set acknowledge data for the last receive.
Page 514 Start Initialize Set MST=0 and TRS=0 in ICCR Set ACKB=0 in ICSR Read IRIC flag in ICCR IRIC=1? Read AAS and ADZ flags in ICSR AAS=1 and General call address processing ADZ=0? *Description omitted Read TRS bit in ICCR Slave transmit mode TRS=0? Last receive? Read ICDR...
Page 515: 23.3.10 Initializing Internal Status
Set transmit data for the second and Slave transmit mode subsequent bytes. Clear IRIC in ICCR Wait for 1 byte to be transmitted. Write transmit data in ICDR Test for end of transfer. Clear IRIC flag in ICCR Select slave receive mode. Dummy read (to release the SCL line).
Page 516 • Internal latches which holds the register read information to set or clear the flags in ICMR, ICCR, ICSR, and DDCSWR • Bit counter (BC2 to BC0) value in ICMR • Sources of interrupts generated (interrupts that has been transferred to the interrupt controller) (2) Notes on Initialization •...
Page 517: Usage Notes
23.4 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition.
Page 518 5. The I C bus interface specification for the SCL rise time t is under 1000 ns (300 ns for high- speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If t (the time for SCL to go from low to V ) exceeds the time determined by the input clock of the I...
Page 519 7. Precautions on reading ICDR at the end of master receive mode When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high level, thereby generating the stop condition.
Page 520 Table 23.7 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Influence Specification φ φ φ φ = 8 MHz φ φ φ φ = 10 MHz Item Indication (Max.) (Min.) −1000 ←...
Page 521: Section 24 A/D Converter
Section 24 A/D Converter 24.1 Overview This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12 analog input channels to be selected. 24.1.1 Features A/D converter has the following features. • 10-bit resolution • 12 input channels •...
Page 522: Block Diagram
24.1.2 Block Diagram Figure 24.1 shows a block diagram of the A/D converter. Internal data bus Reference Voltage 10-bit Hardware control circuit ADTRG (HSW timing generator) Vref ADTRG Chopper type Control circuit comparator φ/2 Sample-and- φ/4 hold circuit Interrupt request [Legend] : Software trigger A/D result register ADTRG, DFG...
Page 523: Pin Configuration
24.1.3 Pin Configuration Table 24.1 summarizes the input pins used by the A/D converter. Table 24.1 A/D Converter Pins Name Abbrev. Function Analog power supply pin Input Analog block power supply and A/D conversion reference voltage Analog ground pin Input Analog block ground and A/D conversion reference voltage Analog input pin 0...
Page 524: Register Configuration
24.1.4 Register Configuration Table 24.2 summarizes the registers of the A/D converter. Table 24.2 A/D Converter Registers Name Abbrev. Size Initial Value Address Software trigger A/D ADRH Byte H'00 H'D130 result register H Software trigger A/D ADRL Byte H'00 H'D131 result register L Hardware trigger A/D AHRH...
Page 525: Register Descriptions
24.2 Register Descriptions 24.2.1 Software-Triggered A/D Result Register (ADR) ADRH ADRL Bit : ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 — — — — — — Initial value : — — — — — — R/W : The software-triggered A/D result register (ADR) is a register that stores the result of an A/D conversion started by software.
Page 526: A/D Control Register (Adcr)
AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 24.3, Interface to Bus Master. AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Page 527 States Instruction execution MOV.B WRITE Start flag Conversion frequency Conversion period (134 or 266 states) Interrupt request flag IRQ sampling (CPU) Note: IRQ sampling; When conversion ends, the start flag is cleared and the interrupt request flag is set. The CPU recognizes the interrupt in the last execution state of an instruction, and executes interrupt exception handling after completing the instruction.
Page 528 Bits 3 to 0    Software Channel Select (SCH3 to SCH0): These bits select the analog input channel that is converted by software triggering. When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode register 0 (PMR0).
Page 529: A/D Control/Status Register (Adcsr)
24.2.4 A/D Control/Status Register (ADCSR) Bit : SEND HEND ADIE BUSY SCNL — Initial value : R/(W)* R/(W)* — R/W : Note: * Only 0 can be written to bits 7 and 6, to clear the flag. The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D conversion, or check the status of the A/D converter.
Page 530 Bit 5    A/D Interrupt Enable (ADIE): Selects enable or disable of interrupt (ADI) generation upon A/D conversion end. Bit 5 ADIE Description Interrupt (ADI) upon A/D conversion end is disabled (Initial value) Interrupt (ADI) upon A/D conversion end is enabled Bit 4...
Page 531 Bit 2    Busy Flag (BUSY): During hardware- or external-triggered A/D conversion, if software attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead the BUSY flag is set to 1. This flag is cleared when the hardware-triggered A/D result register (AHR) is read.
Page 532: Trigger Select Register (Adtsr)
24.2.5 Trigger Select Register (ADTSR) Bit : — — — — — — TRGS1 TRGS0 Initial value : R/W : — — — — — — The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start factor. ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Page 533: Module Stop Control Register (Mstpcr)
Bits 7 to 0    P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): These bits set the P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channel. Bit n PMR0n Description P0n/ANn functions as a general-purpose input port...
Page 534: Interface To Bus Master
24.3 Interface to Bus Master ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
Page 535: Operation
24.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. 24.4.1 Software-Triggered A/D Conversion A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. Conversion can be software-triggered on any of the 12 channels provided by analog input pins AN0 to ANB.
Page 536: Hardware- Or External-Triggered A/D Conversion
24.4.2 Hardware- or External-Triggered A/D Conversion The system contains the hardware trigger function that allows to turn on A/D conversion at a specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the incoming external trigger ($'75*). This function can be used to measure an analog signal that varies in synchronization with an external signal at a fixed timing.
Page 537: Interrupt Sources
24.5 Interrupt Sources When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end interrupt (ADI) can be enabled or disabled by ADIE bit in ADCSR. Figure 24.4 shows the block diagram of A/D conversion end interrupt. A/D control/status register (ADCSR) SEND HEND...
Page 538: Section 25 Address Trap Controller (Atc)
Section 25 Address Trap Controller (ATC) 25.1 Overview The address trap controller (ATC) is capable of generating interrupt by setting an address to trap, when the address set appears during bus cycle. 25.1.1 Features Address to trap can be set independently at three points. 25.1.2 Block Diagram Figure 25.1 shows a block diagram of the address trap controller.
Page 539: Register Configuration
25.1.3 Register Configuration Table 25.1 Register List Name Abbrev. Initial Value Address * Address trap control register ATCR H'F8 H'FFB9 Trap address register 0 TAR0 H'F00000 H'FFB0 to H'FFB2 Trap address register 1 TAR1 H'F00000 H'FFB3 to H'FFB5 Trap address register 2 TAR2 H'F00000 H'FFB6 to H'FFB8...
Page 540 Bit 1    Trap Control 1 (TRC1): Sets ON/OFF operation of the address trap function 1. Bit 1 TRC1 Description Address trap function 1 disabled (Initial value) Address trap function 1 enabled Bit 0    Trap Control 0 (TRC0): Sets ON/OFF operation of the address trap function 0. Bit 0 TRC0 Description...
Page 541: Trap Address Register 2 To 0 (Tar2 To Tar0)
25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) Bit : Initial value : R/W : Bit : Initial value : R/W : Bit : — Initial value : — R/W : The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0) The TAR sets the address to trap.
Page 542: Precautions In Usage
25.3 Precautions in Usage Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur after the trap instruction has been executed, depending on a combination of instructions immediately preceding the setting up of the address trap. If the instruction to trap immediately follows the branch instruction or the conditional branch instruction, operation may differ, depending on whether the condition was satisfied or not, or the address to be stacked may be located at the branch.
Page 543 2. Figure 25.3 shows the operation when the instruction immediately preceding the trap address is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the second state from the last. The address to be stacked is 0268. Start of exception Data instruc-...
Page 544: Enabling
25.3.2 Enabling The address trap function becomes valid after executing one instruction following the setting of the enable bit of the address trap control register (TRCR) to 1. 029C BSET #0, @TRCR MOV.W R0, R1 *029E After executing the MOV instruction, 02A0 MOV.B R1L, R3H the address trap interrupt does not...
Page 545 2. When the condition is not satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction and prefetching the next instruction.
Page 546 3. When condition is not satisfied by Bcc instruction (16-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction (if the trap address instruction is that of 2 states or more.
Page 547 4. When the condition is not satisfied by Bcc instruction (Trap address at branch) When the trap address is at the branch of the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made into the address trap interrupt after executing the next instruction (if the next instruction is that of 2 states or more.
Page 548: Bsr Instruction
25.3.4 BSR Instruction 1. BSR Instruction (8-bit displacement) When the trap address is the next instruction to the BSR instruction and the addressing mode is an 8-bit displacement, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C2. Stack Start of instruc-...
Page 549: Jsr Instruction
25.3.5 JSR Instruction 1. JSR Instruction (Register indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C8. Stack Start of instruc-...
Page 550 2. JSR Instruction (Memory indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02EA. Start of Data Stack...
Page 551: Jmp Instruction
25.3.6 JMP Instruction 1. JMP Instruction (Register indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02AA. Data Start of instruc-...
Page 552: Rts Instruction
2. JMP Instruction (Memory indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02E4. Internal Data Start of...
Page 553: Sleep Instruction
25.3.8 SLEEP Instruction 1. SLEEP Instruction 1 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does not occur in the last state, the SLEEP instruction is not executed and transition is made to the address trap interrupt without going into SLEEP mode.
Page 554 2. SLEEP Instruction 2 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling.
Page 555 3. SLEEP Instruction 3 When the trap address is the next instruction to the SLEEP instruction, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling. The address to be stacked is 0282.
Page 556 4. SLEEP Instruction 4 (Standby or Watch Mode Setting) When the trap address is the SLEEP instruction and the instruction immediately preceding the SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this puts in the standby (watch) mode after execution of the SLEEP instruction.
Page 557: Competing Interrupt
5. SLEEP Instruction 5 (Standby or Watch Mode Setting) When the trap address is the next instruction to the SLEEP instruction, this puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode is cancelled by the NMI interruption, transition is made to the NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector reading.
Page 558 0296 MOV.B R2L, @Port 029A 029C Set one of these to the 029E trap address 02A0 02A2 02A4 Start of general interrupt processing Data Data instruc- instruc- instruc- instruc- tion tion tion tion write read Range of start of ATC pre-fetch pre-fetch pre-fetch...
Page 559 2. In case of NMI When the NMI interruption request is made at the timing in (1) (A) against the ATC interrupt request, the interrupt appears to take place in NMI at the timing earlier than usual, because higher priority is assigned to the NMI interrupt processing. The ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing.
Page 560 Figure 25.22 Competing Interrupt (In Case of NMI) Rev. 1.0, 02/00, page 553 of 1141...
Page 561: Section 26 Servo Circuits
Section 26 Servo Circuits 26.1 Overview 26.1.1 Functions Servo circuits for a video cassette recorder are included on-chip. The functions of the servo circuits can be divided into four groups, as listed in table 26.1. Table 26.1 Servo Circuit Functions Group Function Description...
Page 562 26.1.2 Block Diagram Figure 26.1 shows a block diagram of the servo circuits. PPG0 to 7/ PPG0 to 7/ (P70 to 77) (P70 to 77) RP0 to 7/ RP0 to 7/ (P60 to 67, (P60 to 67, P74 to 77) P74 to 77) EXTTRG(P86) Csync...
Page 563: Block Diagram
26.2 Servo Port 26.2.1 Overview This LSI is equipped with seventeen pins dedicated to the servo circuit and twenty-five pins multiplexed with general-purpose ports. It also has an input amplifier to amplify CTL signals, a CTL output amplifier, a CTL Schmitt comparator, and a CFG zero cross type comparator. The CTL input amplifier allows gain adjustment by software.
Page 564 2. CFG Input Circuit The CFG input pin has an amplifier and a zero cross type comparator. Figure 26.3 shows the input circuit of CFG. P250 VREF CFGCOMP M250 CFGCOMP VREF Res+ModuleSTOP Figure 26.3 CFG Input Circuit Rev. 1.0, 02/00, page 558 of 1141...
Page 565 3. CTL Input Circuit The CTL input pin has an amplifier. Figure 26.4 shows the input circuit of CTL. AMPON AMPSHORT (PB-CTL) (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 PB-CTL(+) PB-CTL(-) CTL( CTL(+) CTLREF CTLBias CTLFB CTLAmp(o) CTLSMT(i) Note Note: Be sure to connect a capacitor between CTLAmp (o) and CTLSMT (i) Figure 26.4 CTL Input Circuit Rev.
Page 566: Pin Configuration
26.2.3 Pin Configuration Table 26.2 shows the pin configuration of the servo circuit. P30, P31, and P81 to P87 are general- purpose ports. As for P3, P6, P7, and P8, see section 10, I/O Port. Table 26.2 Pin Configuration Name Abbrev.
Page 567: Register Configuration
26.2.4 Register Configuration Table 26.3 shows the register configuration of the servo port section. Table 26.3 Register Configuration Name Abbrev. Size Initial Value Address Servo port mode register SPMR Byte H'5F H'D0A0 Servo monitor control register SVMCR Byte H'C0 H'D0A3 CTL gain control register CTLGR Byte...
Page 568 Servo Monitor Control Register (SVMCR) Bit : — — SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 Initial value : R/W : — — SVMCR is an 8-bit read/write register that selects the monitor signal output from the SV1 and SV2 pins when the P30/SV1 pin is used as the SV1 monitor output pin or when the P31/SV2 pin is used as the SV2 monitor output pin.
Page 569 Bits 2 to 0    SV1 Pin Servo Monitor Output Control (SVMCR2 to SVMCR0): Select the servo monitor signal output from the SV1 pin. Bit 2 Bit 1 Bit 0 SVMCR2 SVMCR1 SVMCR0 Description Outputs REF30 signal to SV1 output pin. (Initial value) Outputs CAPREF30 signal to SV1 output pin.
Page 570 Bit 4    SW Bit of the Feedback Section of CTL Amplifier (CTLFB): Turns on or off the switch of the feedback section to adjust the gain. See figure 26.4. Bit 4 CTLFB Description Turns off CTLFB SW (Initial value) Turns on CTLFB SW Bits 3 to 0...
Page 571: Dfg/Dpg Input Signals
26.2.6 DFG/DPG Input Signals DFG and DPG signals can be input either as separate signals or as an overlapped signal. When the latter is selected (PMR87 = 1), take care to control the input levels of DFG and DPG. Figure 26.5 shows DFG/DPG input signals.
Page 572: Reference Signal Generators
26.3 Reference Signal Generators 26.3.1 Overview The reference signal generators consist of a REF30 signal generator and a CREF signal generator and create the reference signals (REF30 and CREF signals) used in phase comparison, etc. The REF30 signal is used to control the phase of the drum and capstan. The CREF signal is used if REF30 signal cannot be used as the reference signal to control the phase of the capstan in REC mode.
Page 573 Figure 26.6 REF30 Signal Generator Rev. 1.0, 02/00, page 567 of 1141...
Page 574: Register Configuration
PB(ASM) ↓ Counter clear DVCFG2 φ Counter (16 bits) φ Clear Match ↑ Edge Comparator (16 bits) Toggle CREF detection Reference period register 2 (16 bits) Reference period buffer 2 (16 bits) Dummy read Internal bus φ s = fosc/2 Figure 26.7 Block Diagram of CREF Signal Generator 26.3.3 Register Configuration...
Page 575: Register Description
26.3.4 Register Description Reference Period Mode Register (RFM) Bit : OD/EV Initial value : R/W : RFM is an 8-bit write-only register which determines the operational state of the reference signal generators. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset and in stand-by and module stop modes.
Page 576 Bit 5    Manual Selection Bit (CVS): Selects whether the REF30 signal is generated synchrously with VD or it is operated in free-run state in the manual mode (VNA = 0). (This selection is ignored in PB mode except in TBC mode.) Bit 5 Description Synchronous with VD...
Page 577 Bit 1    Video FF Counter Set (VST): Selects whether the REF30 counter register value is set on or off by the Video FF signal when the drum phase is in FIX on in the PB mode. Bit 1 Description Counter set off by Video FF signal (Initial value)
Page 578 Reference Period Register 2 (CRF) Bit : CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0 Initial value : R/W : The reference period register 2 (CRF) is an 16-bit write-only buffer register which generates the reference signals to control the capstan phase (CREF).
Page 579 Reference Period Mode Register 2 (RFM2) Bit :       Initial value :       R/W : REM2 is an 8-bit read/write register which determines the operational state of the reference signal generators.
Page 580: Operation
26.3.5 Operation • Operation of REF30 Signal Generator The REF30 signal generator generates the reference signals required to control the phase of the drum and capstan. To generate the REF30 signal, set the 1/2 the reference period to the reference period register 1 (RFD) corresponding to the 50 percent duty cycle.
Page 581 • Timing of the REF30 Signal Generation Figures 26.8 to 26.12 show the timing of the generation of REF30 and REF30P signals. Counter set Counter set Counter set Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) REF30 REF30P...
Page 582 Field signal Selected VD (OD/EV=0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (clear signal mask) About 75% REF30 REF30P Drum phase counter Sampling Sampling Sampling Figure 26.9 Generation of Reference Signal in Record Mode (Normal Operation)
Page 583 Field signal Drop-out of V Selected VD (OD/EV=0) Cleared Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period About 75% About 75% About 75% Counter mask Masking period (clear signal mask) About...
Page 584 Field signal Dislocation of V Selected VD (OD/EV=0) Cleared Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period About 75% About 75% Counter mask Masking period (clear signal mask) About 75% About 75% REF30...
Page 585 External sync signal Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Reset REF30 REF30P Figure 26.12 Generation of REF30 Signal by the External Sync Signal • CREF Signal Generator The CREF signal generator generates the CREF signal which is the reference signal to control the phase of capstan.
Page 586 • Timing Chart of the CREF Signal Generation Figures 26.13 to 26.15 show the generation of CREF signal. Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter Toggle signal CREF Figure 26.13 Generation of CREF Signal Rev. 1.0, 02/00, page 580 of 1141...
Page 587 Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter REC/PB Toggle signal Period set in CRF CREF PB(ASM) Figure 26.14 CREF Signal when PB is Switched to REC (when CRD Bit = 0) Rev. 1.0, 02/00, page 581 of 1141...
Page 588 Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter REC/PB DVCFG2 Toggle signal Period set in CRF CREF PB(ASM) Figure 26.15 CREF Signal when PB is Switched to REC (when CRD Bit = 1) Rev. 1.0, 02/00, page 582 of 1141...
Page 589 Figures 26.16 and 26.17 show REF30 (REF30P) when PB is switched to REC. REC(ASM) Field signal VD (except in PB) Selected VD* (OD/EV=0) REC/PB Value set in reference Cleared Cleared Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask...
Page 590 REC(ASM) Field signal VD (except in PB) Selected VD (OD/EV=0) REC/PB Value set in reference Cleared Cleared period register 1 (RFD) Cleared Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) About Cleared REF30...
Page 591 Figures 26.18 to 26.21 show REF30 (REF30P) when PB is switched to REC (where FDS bit = 1). REC(ASM) REC/PB VD (except in PB) Value set in reference Cleared Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask...
Page 592 REC(ASM) REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) REF30 REF30P FDS bit = 1 Figure 26.19 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (when VD Signal is Not Detected) (2) Rev.
Page 593 REC(ASM) REC/PB VD (except in PB) Value set in reference Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) 25% max. REF30 REF30P FDS bit = 1 Figure 26.20 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (3) Rev.
Page 594 REC(ASM) REC/PB VD (except in PB) Value set in reference Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) 25% max. REF30 REF30P FDS bit = 1 Figure 26.21 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (4) Rev.
Page 595: Hsw (Head-Switch) Timing Generator
26.4 HSW (Head-switch) Timing Generator 26.4.1 Overview The HSW timing generator consists of a 5-bit DFG counter, a 16-bit timer counter, a matching circuit, and two 31-bit 10-stage FIFOs. The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the timing to reset the 16-bit timer counter for each field.
Page 596 Figure 26.22 Block Diagram of the HSW Timing Generator Rev. 1.0, 02/00, page 590 of 1141...
Page 597: Hsw Timing Generator Configuration
26.4.3 HSW Timing Generator Configuration The HSW timing generator is composed of the elements shown in table 26.5. Table 26.5 Configuration of the HSW Timing Generator Element Function HSW mode register 1 (HSM1) Confirmation/determination of this circuits' operating status HSW mode register 2 (HSM2) Confirmation/determination of this circuits' operating status HSW loop stage number setting register...
Page 598: Register Configuration
26.4.4 Register Configuration Table 26.6 shows the register configuration of the HSW timing generator. Table 26.6 Register Configuration Name Abbrev. Size Initial Value Address HSW mode register 1 HSM1 Byte H'30 H'D060 HSW mode register 2 HSM2 Byte H'00 H'D061 HSW loop stage number setting HSLP Byte...
Page 599 Bit 7    FIFO2 Full Flag (FLB): When the FLB bit is 1, it indicates that the FIFO2 is full of the timing pattern data and the output pattern data. If a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the OVWB flag (bit 3) is set to 1, and the write data is lost.
Page 600 Bit 3    FIFO2 Overwrite Flag (OVWB): If a write is attempted when the FIFO2 is full of the timing pattern data and the output pattern data (FLB bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWB flag is set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write again.
Page 601 HSW Mode Register 2 (HSM2) Bit : FGR2OFF ISEL1 SOFG VFF/NFF Initial value : R/W : HSM2 is an 8-bit register which confirms and determines the operational state of the HSW timing generator. Bit 1 is a read-only bit, and write is disabled. Bit 0 is a write-only bit, and if a read is attempted, an undetermined value is read out.
Page 602 Bit 4    DFG Edge Selection Bit (EDG): Selects the edge by which to count DFG pulses. Bit 4 Description Counts by the rising edge of DFG (Initial value) Counts by the falling edge of DFG Bit 3    Interrupt Selection Bit (ISEL1): Selects the interrupt source. (IRRHSW1) Bit 3 ISEL1 Description...
Page 603 Bit 0    Output Switching Bit Between VideoFF and NarrowFF (VFF/NFF): Switches the signal output from the VideoFF pin. Bit 0 VFF/NFF Description VideoFF output (Initial value) NarrowFF output HSW Loop Stage Number Setting Register (HSLP) Bit : LOB3 LOB2 LOB1...
Page 604 Bits 7 to 4    FIFO2 Stage Number Setting Bits (LOB3 to LOB0): Set the number of FIFO2 stages in loop mode. They are valid only when the loop mode is set (LOP bit of HSM2 is 1). HSM2 HSLP Bit 5...
Page 605 Bits 3 to 0    FIFO1 Stage Number Setting Bits (LOA3 to LOA0): Set the number of FIFO1 stages in loop mode. They are valid only when the loop mode is set (LOP bit of HSM2 is 1). HSM2 HSLP Bit 5...
Page 606 FIFO Output Pattern Register 1 (FPDRA) Bit : ADTRGA STRIGA NarrowFFA VFFA AFFA VpulseA MlevelA — Initial value : — R/W : Bit : PPGA7 PPGA6 PPGA5 PPGA4 PPGA3 PPGA2 PPGA1 PPGA0 Initial value : R/W : Note : * Don't care FPDRA is a buffer register for the FIFO1 output pattern register.
Page 607 FIFO Output Pattern Register 2 (FPDRB) Bit : — ADTRGB STRIGB NarrowFFB VFFB AFFB VpulseB MlevelB Initial value : — R/W : Bit : PPGB7 PPGB6 PPGB5 PPGB4 PPGB3 PPGB2 PPGB1 PPGB0 Initial value : R/W : Note : * Don't care FPDRB is a buffer register for the FIFO2 output pattern register.
Page 608 FIFO Timing Pattern Register 1 (FTPRA) Bit : FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8 Initial value : R/W : Bit : FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0 Initial value : R/W : Note : * Don't care FTPRA is a register to write the timing pattern data of FIFO1.
Page 609 DFG Reference Register 1 (DFCRA) Bit : ISEL2 CCLR CKSL DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0 Initial value : R/W : Note : * Don't care DFCRA is a register which determines the operation of the HSW timing generator as well as the starting point of the timing of FIFO1.
Page 610 Bit 5    16-bit Timer Counter Clock Source Selection Bit (CKSL): Selects the clock source of the 16-bit timer counter. Bit 5 CKSL Description φs/4 (Initial value) φs/8 Bits 4 to 0    FIFO1 Output Timing Setting Bits (DFCRA4 to DFCRA0): Determines the starting point of the timing of FIFO1.
Page 611 FIFO Timer Capture Register (FTCTR) Bit : FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 Initial value : R/W : Bit : FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0 Initial value : R/W : FTCRT is a register to display the count of the 16-bit timer counter. FTCRT is an 16-bit read-only register.
Page 612: Operation
26.4.6 Operation 5-Bit DFG Counter: The 5-bit DFG counter increments the count at the DFG edges selected by the EDG bit of HSW Mode Register 2. The DFG counter is cleared by a DPG rising edge, or by writing to the CCLR bit of the DFG reference register 1. 16-Bit Timer Counter: The 16-bit timer counter can operate in DFG reference mode or in free- running mode.
Page 613 • Loop Mode The data output cycle is repeated from stage 0 to the final stage selected in the HSW loop number setting register. As in single mode, the output pattern data is output when the timing pattern matches the counter value. In loop mode, the FIFO data is retained. Data in each FIFO group can be modified in loop mode.
Page 614 Figure 26.23 Example of Timing Waveform of HSW (for 12 DFG Pulses) Rev. 1.0, 02/00, page 608 of 1141...
Page 615 Internal bus FPDRA FPDRB FTPRA FTPRB FIFO1 FIFO2 Output select buffer Output data buffer Comparator φ Timer counter Output pattern data Figure 26.24 Example of Operation of the HSW Timing Generator Rev. 1.0, 02/00, page 609 of 1141...
Page 616 • Example of operation in single mode (20 stages of FIFO used) 1 Set to single mode (LOP = 0) 2 Write the output pattern data (PA0) to FPDRA. 3 Write the output timing (t ) to FTPRA. t is written in FIFO1 together with PA0. This initializes the output pattern data to PA0.
Page 617 • Example of the operation in loop mode mode 1 Set the number of loop stages in HSLP register (e.g. HSLP = H'44) 2 Write the output pattern data (PA0) to FPDRA. 3 Write the output timing (t ) to FTPRA. t is written in FIFO1 together with PA0.
Page 618: Interrupts
26.4.7 Interrupts The HSW timing generator generates interrupts under the following conditions. 1 IRRHSW1 occurs when pattern data is written (OVWA, OVWB = 1) while FIFO is full (FULL). 2 IRRHSW1 occurs when matching is detected while the STRIG bit of FIFO is 1. 3 IRRHSW1 occurs when the values of the 16-bit timer counter and 16-bit timing pattern register match.
Page 619: Cautions
26.4.8 Cautions • When both the 5-bit DFG counter and 16-bit timer counter are operating, the latter is not cleared if input of DPG and DFG signals is stopped. This leads to free-running of the 16-bit timer counter, and periodical detection of matching by the 16-bit timer counter. In such a case, the period of the output from the HSW timing generator is independent from DPG or DFG.
Page 620: High-Speed Switching Circuit For Four-Head Special Playback
26.5 High-Speed Switching Circuit for Four-Head Special Playback 26.5.1 Overview This high-speed switching circuit generates a color rotary signal (C.Rotary) and head-amplifier switching signal (H.Amp SW) for use in four-head special playback. A pre-amplifier output comparison result signal is input from the COMP pin. The signal output to the C.Rotary pin is a chroma signal processing control signal.
Page 621: Pin Configuration
26.5.3 Pin Configuration Table 26.7 summarizes the pin configuration of the high-speed switching circuit for four-head special playback. If this circuit is not used, the pins can be used as I/O port. See section 26.2, Servo Port. Table 26.7 Pin Configuration Name Abbrev.
Page 622 Special Playback Control Register (CHCR) Bit : HSWPOL SIG3 SIG2 SIG1 SIG0 Initial value : R/W : CHCR is an 8-bit write-only register. It cannot be read. It is initialized to H'00 by a reset, or in standby or module stop mode. Bits 7...
Page 623 Bit 4    H.AmpSW Synchronization Control Bit (HAH): Synchronizes H.AmpSW signal with the OSCH signal. Bit 4 Description Synchronous (Initial value) Asynchronous Bits 3 to 0    Signal Control (SIG3 to SIG0): These bits, combined with the state of the COMP input pin, control the outputs at the C.Rotary and H.AmpSW pins.
Page 624: Drum Speed Error Detector
26.6 Drum Speed Error Detector 26.6.1 Overview Drum speed error control holds the drum at a constant revolution speed, by measuring the period of the DFG signal. A digital counter detects the speed error against a preset value. The speed error data is processed and added to phase error data in a digital filter.
Page 625 Figure 26.27 Block Diagram of the Drum Speed Error Detector Rev. 1.0, 02/00, page 619 of 1141...
Page 626: Register Configuration
26.6.3 Register Configuration Table 26.9 shows the register configuration of the drum speed error detector. Table 26.9 Register Configuration Name Abbrev. Size Initial Value Address Specified DFG speed DFPR Word H'0000 H'D030 preset data register DFG speed error data DFER Word H'0000 H'D032...
Page 627: Register Description
26.6.4 Register Description Specified DFG Speed Preset Data Register (DFPR) Bit : DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8 Initial value : R/W : Bit : DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0 Initial value : R/W : The DFG speed preset data is set in DFPR.
Page 628 DFG Speed Error Data Register (DFER) Bit : DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8 Initial value : R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Bit : DFER7 DFER6 DFER5 DFER4 DFER3 DFER2 DFER1 DFER0 Initial value : R/W : R*/W R*/W...
Page 629 DFG Lock LOWER Data Register (DFRLDR) Bit : DFRLDR15 DFRLDR14 DFRLDR13 DFRLDR12 DFRLDR11 DFRLDR10 DFRLDR9 DFRLDR8 Initial value : R/W : Bit : DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0 Initial value : R/W : DFRLDR is a 16-bit write-only register used to set the lock range on the LOWER side when drum speed lock is detected, and to set the limit value on LOWER side when limiter function is in use.
Page 630 Bits 7 and 6    Clock Source Selection Bits (DFCS1, DFCS0): DFCS1 and DFCS0 select the clock to be supplied to the counter. (φs = fosc/2) Bit 7 Bit 6 DFCS1 DFCS0 Description φs (Initial value) φs/2 φs/4 φs/8 Bit 5...
Page 631 Bit 2    Drum Phase System Filter Computation Automatic Start Bit (DPCNT): Enables the filter computation of the phase system if an underflow occurred in the drum lock counter. Bit 2 DPCNT Description Disables the filter computation by detection of the drum lock. (Initial value) Enables the filter computation of the phase system when drum lock is detected.
Page 632: Operation
26.6.5 Operation The drum speed error detector detects the speed error based on the reference value set in the DFG specified speed preset register (DFPR). The reference value set in DFPR is preset in the counter by NCDFG signal, and the counter decrements the count by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of NCDFG signal.
Page 633 • Interrupt request IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection counter. IRRDRM2 is generated by detection of lock (after the detection of the specified number of times of locking). NCDFG signal Error data latch signal (DFG ↑) Preset data load signal...
Page 634 26.6.6 Correction in Trick Play Mode In trick play mode, the tape speed relative to the video head changes. This change alters the horizontal sync signal (f ), causing skew. To correct the skew, the drum motor speed must be shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync frequency.
Page 635: Drum Phase Error Detector
26.7 Drum Phase Error Detector 26.7.1 Overview The drum phase control system must start after the drum motor has reached the specified revolution speed by the speed control system. Drum phase control works as follows in record and playback mode. •...
Page 636: Block Diagram
26.7.2 Block Diagram Figure 26.29 shows a block diagram of the drum phase error detector. Figure 26.29 Block Diagram of Drum Phase Error Detector Rev. 1.0, 02/00, page 630 of 1141...
Page 637: Register Configuration
26.7.3 Register Configuration Table 26.10 shows the register configuration of the drum phase error detector. Table 26.10 Register Configuration Name Abbrev. Size Initial Value Address Specified drum phase DPPR1 Byte H'F0 H'D03C preset data register 1 Specified drum phase DPPR2 Word H'0000 H'D03A...
Page 638: Register Description
26.7.4 Register Description Drum Phase Preset Data Registers (DPPR1, DPPR2) DPPR1 Bit : — — — — DPPR19 DPPR18 DPPR17 DPPR16 Initial value : — — — — R/W : DPPR2 Bit : DPPR15 DPPR14 DPPR13 DPPR12 DPPR11 DPPR10 DPPR9 DPPR8 Initial value : R/W :...
Page 639 Drum Phase Error Data Registers (DPER1, DPER2) DPER1 Bit : — — — — DPER19 DPER18 DPER17 DPER16 Initial value : — — — — R*/W R*/W R*/W R*/W R/W : DPER2 Bit : DPER15 DPER14 DPER13 DPER12 DPER11 DPER10 DPER9 DPER8 Initial value :...
Page 640 Drum Phase Error Detection Control Register (DPGCR) Bit : DPCS1 DPCS0 DPOVF HSWES — — — Initial value : — — — R/(W)* R/W : Note: Only 0 can be written. DPGCR is an 8-bit read/write register that controls the operation of drum phase error detection. Bits 2-0 are reserved, bit 5 accepts only read and 0 write.
Page 641: Operation
Bit 3    Edge Selection Bit (HSWES): Selects the edge of the error data latch signal (HSW or NHSW). Bit 3 HSWES Description Latches at the rising edge (Initial value) Latches at the falling edge Bits 2 to 0    Reserved: Cannot be modified and are always read as 1. 26.7.5 Operation The drum phase error detector detects the phase error based on the reference value set in the drum...
Page 642 REF30P HSW (NHSW)* Preset Preset Counter Latch Latch Preset value Preset value Note: Edge selectable Figure 26.30 Drum Phase Control in Playback Mode (HSW Rising Edge Selected) Reset Reset REF30P HSW (NHSW)* Preset Preset Counter Latch Latch Preset value Preset value Note: Edge selectable Figure 26.31 Drum Phase Control in Record Mode (HSW Rising Edge Selected) Rev.
Page 643: Phase Comparison
26.7.6 Phase Comparison The phase comparison circuit measures the difference of time between the reference signal and the comparing signal with a digital counter. REF30 signal is used for the reference signal, and HSW signal (VideoFF) or NHSW signal (NarrowFF) from the HSW timing generator is used for the comparing signal.
Page 644: Capstan Speed Error Detector
26.8 Capstan Speed Error Detector 26.8.1 Overview Capstan speed control holds the capstan motor at a constant revolution speed, by measuring the period of the CFG signal. A digital counter detects the speed error against a preset value. The speed error data is added to phase error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase of the capstan motor.
Page 645: Block Diagram
26.8.2 Block Diagram Figure 26.32 shows a block diagram of the capstan speed error detector. Figure 26.32 Block Diagram of Capstan Speed Error Detector Rev. 1.0, 02/00, page 639 of 1141...
Page 646: Register Configuration
26.8.3 Register Configuration Table 26.11 shows the register configuration of the capstan speed error detector. Table 26.11 Register Configuration Name Abbrev. Size Initial Value Address Specified CFG speed CFPR Word H'0000 H'D050 preset data register CFG speed error data CFER Word H'0000 H'D052...
Page 647: Register Description
26.8.4 Register Description Specified CFG Speed Preset Data Register (CFPR) Bit : CFPR15 CFPR14 CFPR13 CFPR12 CFPR11 CFPR10 CFPR9 CFPR8 Initial value : R/W : Bit : CFPR7 CFPR6 CFPR5 CFPR4 CFPR3 CFPR2 CFPR1 CFPR0 Initial value : R/W : The 16-bit preset data that defines the specified CFG speed is set in CFPR.
Page 648 CFG Speed Error Data Register (CFER) Bit : CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8 Initial value : R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Bit : CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0 Initial value : R/W : R*/W R*/W...
Page 649 CFG Lock LOWER Data Register (CFRLDR) Bit : CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8 Initial value : R/W : Bit : CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0 Initial value : R/W : CFRLDR is a 16-bit write-only register used to set the lock range on the LOWER side when capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is in use.
Page 650 Bits 7 and 6    Clock Source Selection Bits (CFCS1, CFCS0): CFCS1 and CFCS0 select the clock to be supplied to the counter. (φs = fosc/2) Bit 7 Bit 6 CFCS1 CFCS0 Description φs (Initial value) φs/2 φs/4 φs/8 Bit 5...
Page 651 Bit 2    Capstan Phase System Filter Computation Automatic Start Bit (CPCNT): Enables the filter computation of the phase system if an underflow occurred in the capstan lock counter. Bit 2 CPCNT Description Disables the filter computation by detection of the capstan lock. (Initial value) Enables the filter computation of the phase system when capstan lock is detected.
Page 652: Operation
26.8.5 Operation The capstan speed error detector detects the speed error based on the reference value set in the CFG specified speed preset register (CFPR). The reference value set in CFPR is preset in the counter by the DVCFG signal, and the counter decrements the count by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of DVCFG signal.
Page 653 Error data latch signal (DVCFG) Preset data load signal Preset period Specified speed value (2 counts) Counter –value +value Preset value Latch data 0 (no error) Figure 26.33 Example of the Capstan Speed Error Detection Rev. 1.0, 02/00, page 647 of 1141...
Page 654: Capstan Phase Error Detector
26.9 Capstan Phase Error Detector 26.9.1 Overview The capstan phase control system must start operation after the capstan motor has reached the specified speed by the speed control system. The capstan phase control system operates as follows in record/playback mode: •...
Page 655 Figure 26.34 Block Diagram of Capstan Phase Error Detector Rev. 1.0, 02/00, page 649 of 1141...
Page 656: Register Configuration
26.9.3 Register Configuration Table 26.12 shows the register configuration of the capstan phase error detector. Table 26.12 Register Configuration Name Abbrev. Size Initial Value Address Specified Capstan phase CPPR1 Byte H'F0 H'D05C preset data register 1 Specified Capstan phase CPPR2 Word H'0000 H'D05A...
Page 657: Register Description
26.9.4 Register Description Specified Capstan Phase Preset Data Registers (CPPR1, CPPR2) CPPR1 Bit : — — — — CPPR16 CPPR19 CPPR18 CPPR17 Initial value : — — — — R/W : CPPR2 Bit : CPPR15 CPPR14 CPPR13 CPPR12 CPPR11 CPPR10 CPPR9 CPPR8 Initial value :...
Page 658 Capstan Phase Error Data Registers (CPER1, CPER2) Bit : — — — — CPER19 CPER18 CPER17 CPER16 Initial value : R*/W R*/W R*/W R*/W R/W : — — — — Bit : CPER15 CPER14 CPER13 CPER12 CPER11 CPER10 CPER9 CPER8 Initial value : R*/W R*/W...
Page 659 Capstan Phase Error Detection Control Register (CPGCR) Bit : — — — CPCS1 CPCS0 CPOVF CR/RF SELCFG2 Initial value : — — — R/(W)* R/W : Note: Only 0 can be written CPGCR is an 8-bit read/write register that controls the operation of capstan phase error detection. Bits 2-0 are reserved, and bit 5 accepts only read and 0 write.
Page 660: Operation
Bit 3    Latch Signal Selection Bit (SELCFG2): Selects the counter preset signal and the error data latch signal data in PB (ASM) mode. Bit 3 SELCFG2 Description Presets CAPREF30 signal; latches DVCTL signal (Initial value) Presets REF30P (CREF) signal; latches DVCFG2 signal Bits 2 to 0...
Page 661 CAPREF30 PB-CTL DVCTL DVCFG2 Preset Preset Counter Latch Latch Preset value Figure 26.35 Capstan Phase Control in Playback Mode REF30P CREF DVCFG2 Preset Preset Counter Latch Latch Preset value Figure 26.36 Capstan Phase Control in Record Mode Rev. 1.0, 02/00, page 655 of 1141...
Page 662: X-Value And Tracking Adjustment Circuit
26.10 X-Value and Tracking Adjustment Circuit 26.10.1 Overview To maintain compatibility with other VCRs, an on-chip adjustment circuit adjusts the phase of the reference signal (internal reference signal (REF30) or external reference signal (EXCAP)) during playback. Because of manufacturing tolerances, the physical distance between the video head and control head (the X-value: 79.244 mm) may vary from set to set, so when a tape that was recorded on a different set is played back, the phase of the reference signal may need to be adjusted.
Page 663 Figure 26.37 Block Diagram of X-Value Adjustment Circuit Rev. 1.0, 02/00, page 657 of 1141...
Page 664: 26.10.3 Register Description
26.10.3 Register Description Register Configuration Table 26.13 shows the register configuration of X-value correction and tracking correction circuits. Table 26.13 Register Configuration Name Abbrev. Size Initial Value Address X-value and TRK-value XTCR Byte H'80 H'D074 control register X-value data register Word H'F000 H'D070...
Page 665 Bit 5    Capstan Phase Correction Auto/Manual Selection Bit (AT/08 08): Selects whether the generation of the correction reference signal (CAPREF30) for capstan phase control is controlled automatically or manually depending on the status of the ASM and REC/3% bits of CTL mode register.
Page 666 Bits 1 and 0    REF30P Division Ratio Selection Bit (DVREF1, DVREF0): Selects the division value of REF30P. If it is read-accessed, the counter value is read out. (The selected division value is set by the UDF of the counter.) Bit 1 Bit 0 DVREF1...
Page 667: Digital Filters
26.11 Digital Filters 26.11.1 Overview The digital filters required in servo control make extensive use of multiply-accumulate operations on signed integers (error data) and coefficients. A filter computation circuit (digital filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to improve processing efficiency.
Page 668: 26.11.2 Block Diagram
26.11.2 Block Diagram Error latch signal Accumulator Accumulation Error check controller Accumulation sequence circuit Start Data LA (16 bits), Buffer/ shifter lower accumulator register select & Sign UA (32 bits), controller A, B, G, etc. upper accumulator Write-only MD (32 bits), multiplied data Read-only Buffer circuit...
Page 669 Figure 26.39 Digital Filter Representation Rev. 1.0, 02/00, page 663 of 1141...
Page 670: 26.11.3 Arithmetic Buffer
26.11.3 Arithmetic Buffer This buffer stores computational data used in the digital filters. See table 26.14. Write access is limited to the gain and coefficient data (Z ). The other data is used by hardware. None of the data can be read. Table 26.14 Arithmetic Buffer Register Configuration Buffer Data Length Arithmetic...
Page 671: Register Configuration
26.11.4 Register Configuration Table 26.15 shows the register configuration of the digital circuit. Table 26.15 Register Configuration Name Abbrev. Size Initial Value Address Capstan phase gain CGKp Word Undetermined H'D010 constant Capstan speed gain CGKs Word Undetermined H'D012 constant Capstan phase coefficient A Word Undetermined H'D014...
Page 672: 26.11.5 Register Description
26.11.5 Register Description Gain Constants (DGKp, DGKs, CGKp, CGKs) Bit : Initial value : R/W : Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set accumulation gain of the digital filter. Only a word access is valid. Accumulation gain can be set to gain 1 value as maximum value. If a byte access is attempted, correct operation is not guaranteed.
Page 673 Offset (DOfp, DOfs, COfp, COfs) Bit : Initial value : R/W : Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set offset level of digital filter output. Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a read is attempted, an undetermined value is read out.
Page 674 Drum System Digital Filter Control Register (DFIC) Bit : DROV DPHA DZPON DZSON DSG2 DSG1 DSG0 — Initial value : — R/(W)* R/(W) R/W : Note: * Only 0 can be written DFIC is an 8-bit read/write register that controls the status of the drum digital filter and operating mode.
Page 675 Bit 4    Drum Phase System Z Initialization Bit (DZPON): Reflects the DZp value on Z of the phase system when computation processing of the drum phase system begins. If 1 is written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp. Bit 4 DZPON Description...
Page 676 Capstan System Digital Filter Control Register (CFIC) Bit : — CROV CPHA CZPON CZSON CSG2 CSG1 CSG0 Initial value : — R/W : R/(W)* R/(W) Note: * Only 0 can be written CFIC is an 8-bit read/write register that controls the status of the capstan digital filter and operating mode.
Page 677 Bit 4    Capstan Phase System Z Initialization Bit (CZPON): Reflects the CZp value on Z the capstan phase system when computation processing of the phase system begins. If 1 is written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZp.
Page 678 Digital Filter Control Register (DFUCR) Bit : — — PTON CP/DP CFEPS DFEPS CFESS DFESS Initial value : — — R/W : DFUCR is an 8-bit read/write register which controls the operation of the digital filter. Only a byte access is valid. If a word access is attempted, correct operation is not guaranteed. It is initialized to H'00 by a reset, or in stand-by or module stop mode.
Page 679 Bit 3    Capstan Phase System Error Data Transfer Bit (CFEPS): Transfers the capstan phase system error data to the digital filter when the data write is enforced. Bit 3 CFEPS Description Error data is transferred by DVCFG2 signal latching. (Initial value) Error data is transferred when the data is written.
Page 680: 26.11.6 Filter Characteristics
26.11.6 Filter Characteristics • Lag-Lead Filter A filter required for a servo loop is built in the hardware. This filter uses IIR (infinite impulse response) type digital filter (another type of the digital filter is FIR, i.e. finite impulse response type).
Page 681 • Frequency Characteristics The computation circuit repeats computation of the function, which is obtained by s-z conversion according to bi-linear approximation of the transfer function on the s-plane. Figure 26.41 shows the frequency characteristics of the lag-lead filter. 20log(f1/f2) Frequency (Hz) Figure 26.41 Frequency Characteristics of the Lag-Lead Filter The pulse transfer function G (Z) is obtained by the bi-linear approximation of the transfer G (S).
Page 682: 26.11.7 Operations In Case Of Transient Response
26.11.7 Operations in Case of Transient Response In case of transient response when the motor is activated, the digital filter computation circuit must prevent computation due to a large error. The convergence of the computations becomes slow and servo retraction deteriorates if a large error is input to the filter circuit when it is performing repeated computations.
Page 683 Usn-1 DZs11 to 0 DZp11 to 0 CZs11 to 0 Delay initialization CZp11 to 0 register DAs15 to 0 DBs15 to 0 DAp15 to 0 DBp15 to 0 CAs15 to 0 CBs15 to 0 initiali- CAp15 to 0 CBp15 to 0 zation bit DZSON DZPON...
Page 684: Additional V Signal Generator
26.12 Additional V Signal Generator 26.12.1 Overview The additional V signal generator outputs an additional vertical sync signal to take the place of Vsync in special playback. It is activated at both edges of the HSW signal output by the head- switch timing generator.
Page 685: Pin Configuration
26.12.2 Pin Configuration Table 26.16 summarizes the pin configuration of the additional V signal. Table 26.16 Pin Configuration Name Abbrev. Function Additional V pulse pin Vpulse Output Output of additional V signal synchronized to video FF 26.12.3 Register Configuration Table 26.17 summarizes the register that controls the additional V signal. Table 26.17 Register Configuration Name Abbrev.
Page 686 Bit 3    High Impedance (HiZ): Set to 1 when the intermediate level is generated by an external circuit. Bit 3 Description Vpulse is a three-level output pin (Initial value) Vpulse is a three-state output pin (high, low, or high-impedance) Bits 2 to 0...
Page 687: 26.12.5 Additional V Pulse Signal
26.12.5 Additional V Pulse Signal Figure 26.44 shows the additional V pulse signal. The M level and V pulse signals are generated by the head-switch timing generator. The OSCH signal is combined with these to produce equalizing pulses. The polarity can be selected by the POL bit in the additional V control register (ADDVR).
Page 688 Additional V Pulses When Sync Signal is Not Detected: With additional V pulses, the pulse signal (OSCH) detected by the sync signal detector is superimposed on the V pulse and Mlevel signals generated by the head-switch timing generator. If there is a lot of noise in the input sync signal (Csync), or a pulse is missing, OSCH will be a complementary pulse, and therefore an H pulse of the period set in HRTR and HPWR will be superimposed.
Page 689 HSW signal edge M level signal V pulse signal OSCH Additional V pulse VPON=1, CUT=0, POL=0 Figure 26.46 Additional V Pulse When Negative Polarity Is Specified Rev. 1.0, 02/00, page 683 of 1141...
Page 690: Ctl Circuit
26.13 CTL Circuit 26.13.1 Overview The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then outputs it as the PB-CTL signal to the servo, linear time counter, and other circuits. The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and records VISS, ASM, and VASS marks.
Page 691: 26.13.2 Block Diagram
26.13.2 Block Diagram Figure 26.47 shows a block diagram of the CTL circuit. PB-CTL CTL mode IRRCTL Duty dis- VISS detect FW/RV criminator VISS control circuit detector VISS write REF30X Bit pattern register Write control circuit Duty I/O flag Internal bus Schmitt amplifier REC-...
Page 692: Pin Configuration
26.13.3 Pin Configuration Table 26.18 summarizes the pin configuration of the CTL circuit. Table 26.18 Pin Configuration Name Abbrev. Function CTL (+) I/O pin CTL (+) CTL signal input/output CTL (–) I/O pin CTL (–) CTL signal input/output CTL bias input pin CTL Bias Input CTL primary amplifier bias supply...
Page 693: 26.13.5 Register Description
26.13.5 Register Description CTL Control Register (CTCR) Bit : NT/PL FSLC FSLB FSLA LCTL UNCTL SLWM Initial value : R/W : CTCR is an 8-bit read/write register that controls PB-CTL rewrite and sets the slow mode. When CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register (CTLGR) in PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1.
Page 694 Bits 3    Clock Source Select Bit (CCS): Selects clock source of CTL. Bit 3 Description φs (Initial value) φs/2 Bit 2    Long CTL Bit (LCTL): Sets the long CTL detection mode. Bit 2 LCTL Description Clock source (CCS) operates at the setting value (Initial value)
Page 695 CTL Mode Register (CTLM) Bit : REC/PB FW/RV Initial value : R/W : CTLM is an 8-bit read/write register that controls the operating state of the CTL circuit. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later. CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode.
Page 696 CTL input PB-CTL Figure 26.48 Internal PB-CTL Signal in Forward and Reverse Bits 4 to 0    CTL Mode Select (MD4 to MD0): These bits select the detect, record, and rewrite modes for VISS, VASS, and ASM marks. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later.
Page 697 R/3 3 3 3 Mode Description • The duty I/O flag is set to 1 at VISS detect the point of write access to (index register CTLM detect) • The 1 pulses recognized by the duty discrimination circuit are counted in the VISS control circuit •...
Page 698 REC-CTL Duty Data Register 1 (RCDR1) Bit : — — — — CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 Initial value : — — — — R/W : RCDR1 is a 12-bit write-only register that sets the REC-CTL rising timing. This setting is valid only for recording and rewriting, and is not used in detection.
Page 699 REC-CTL Duty Data Register 2 (RCDR2) Bit : — — — — CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 Initial value : — — — — R/W : RCDR2 is a 12-bit write-only register that sets 1 pulse (short) falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting.
Page 700 REC-CTL Duty Data Register 3 (RCDR3) Bit : — — — — CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 Initial value : R/W : — — — — RCDR3 is a 12-bit write-only register that sets 1 pulse (long) and assemble mark falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting.
Page 701 REC-CTL Duty Data Register 4 (RCDR4) Bit : — — — — CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 Initial value : — — — — R/W : RCDR4 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of REC-CTL in record or rewrite mode.
Page 702 REC-CTL Duty Data Register 5 (RCDR5) Bit : — — — — CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 Initial value : R/W : — — — — RCDR5 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of REC-CTL in record or rewrite mode.
Page 703 Duty I/O Register (DI/O) Bit : — VCTR2 VCTR1 VCTR0 BPON DI/O Initial value : — R/(W)* R/W : Note: * Only 0 can be written DI/O is an 8-bit register that confirms and determines the operating status of the CTL circuit. It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode.
Page 704 Bit 3    Bit Pattern Detection ON/OFF Bit (BPON): Determines ON or OFF of bit pattern detection. Note: When writing 1 to BPON bit, be sure to set appropriate data to RCDR 2 to 5 beforehand. Bit 3 BPON Description Bit pattern detection off...
Page 705 • VISS Detect Mode and VASS Detect Mode: The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is above 44% (a 0 pulse in the CTL signal). The duty I/O flag is 0 when the duty cycle of the PB-CTL signal is below 44% (a 1 pulse in the CTL signal).
Page 706 Bit Pattern Register (BTPR) Bit : LSP7 LSP6 LSP5 LSP4 LSP3 LSP2 LSP1 LSP0 Initial value : R/W : R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Write is prohibited when bit pattern detection is selected. BTPR is an 8-bit shift register which detects and records the bit pattern of the CTL pulses. If a CTL pulse is detected in PB or ASM mode, the register is shifted leftward at the rising edge of PB-CTL, and reflects the determined result of long/short on the bit 0 (long pulse = 1, short pulse = If BPON bit is set to 1 in PB mode, the register starts detection of bit pattern immediately after the...
Page 707: 26.13.6 Operation
26.13.6 Operation CTL Circuit Operation: As shown in figure 26.49, the CTL discrimination/record circuit is composed of a 16-bit up/down counter and 12-bit registers (×5). In playback (PB) mode, the 16-bit up/down counter counts on a φs/4 clock when the PB-CTL pulse is high, and on a φs/5 clock when low.
Page 708 The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle REF30P X-value Latch after Preset change X-value Capstan phase control ASM mode, PB mode : REF30X-PB-CTL REC mode : REF30P-DVCFG2...
Page 709 The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle REF30P X-value after change X value Capstan phase control ASM mode, PB mode: REF30X-PB-CTL REF30X PB-CTL REC-CTL...
Page 710: 26.13.7 Ctl Input Section
26.13.7 CTL Input Section The CTL input section consists of an input amplifier of which gain can be controlled by the register setting and a Schmitt amplifier. Figure 26.52 shows a block diagram of the CTL input section. Trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier, reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits, and the Timer L as the PB-CTL signal.
Page 711 CTL Detector: If the CTL detector fails to detect a CTL pulse, it sets the CTL control register (CTCR) bit 1 to 1 indicating that the pulse has not been detected. If a CTL pulse is detected after that, the bit is automatically cleared to 0. Duration used for determining detection or non- detection of the pulse depends on magnitude of phase shift of the last detected pulse from the reference phase (phase difference between REF30 and CTL signal).
Page 712 PB-CTL Waveform Shaper in Slow Mode Operation: If bit 0 in CTL control register (CTCR) is set to slow mode, slow reset function is activated. In slow mode, if falling edge is not detected within the specified time from rising edge detection, PB-CTL is forcibly shut down (slow reset). The time T (s) until the signal falls is the following interval after the rising edge of the internal CTL signal is detected:...
Page 713: 26.13.8 Duty Discriminator
26.13.8 Duty Discriminator The duty discriminator circuit measures the period of the control signal recorded on the tape (PB- CTL signal) and discriminates its duty cycle. In VISS or VASS detection, the duty I/O flag is set or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when the duty cycle of the PB-CTL signal is above 44%, and is cleared to 0 when the duty cycle is below 44%.
Page 714 Input signal Short 1 pulse PB-CTL 25±0.5% Input signal Long 1 pulse PB-CTL 30±0.5% Input signal Short 0 pulse PB-CTL 57.5±0.5% Input signal Long 0 pulse PB-CTL 62.5±0.5% Input signal ASM mark PB-CTL 67 to 70% Figure 26.55 PB-CTL Signal Duty Cycle Rev.
Page 715 Figure 26.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by counting with the 16-bit up/down counter, using a φs/4 clock for the up-count and a φs/5 clock for the down-count. An up-count is performed when the PB-CTL signal is high, and a down-count when low.
Page 716 VISS (Index) Detect Mode: VISS detection is carried out by the VISS control circuit, which counts 1 pulses in the PB-CTL signal. If the pulse count detects any value set in the VISS interrupt setting bits (bits 5, 6, or 7 in the duty I/O register), an interrupt request is generated and the duty I/O flag is cleared to 0.
Page 717 Duty Detection Mode (VASS): VASS detection is carried out by the duty discriminator. Software can detect index sequences by reading the duty I/O flag at each CTL pulse. At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty I/O flag, and simultaneously generates an interrupt request.
Page 718 Detection of the Long/Short Pulse: The long/short pulse is detected in PB mode by the L/S determination based on the comparison of the REC-CTL duty register (RCDR2 to RCDR5) with the up/down counter and the results of the duty I/O flag. The results of the determination is stored in bit 0 (LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting at the same time BTPR leftward.
Page 719: 26.13.9 Ctl Output Section
26.13.9 CTL Output Section An on-chip control head amplifier is provided for writing the REC-CTL signal generated by the write control circuit onto the tape. The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS and VASS sequences and ASM marks and the rewriting of VISS and VASS sequences.
Page 720 Internal bus RESET REF30X↑ Clear RCDR1 RCDR2or4 RCDR3or5 φs/4 UP/DOWN counter (12 bits) (12 bits) (12 bits) (12 bits) Upper 12 bits Compare Compare Compare REC-CTL rise timing REC-CTL1 pulse, REC-CTL 0 pulse fall ASM fall timing timing End of writing of one CTL pulse (except VISS) IRRCTL REF30X Counter...
Page 721 The 16-bit counter in the REC-CTL circuit continues counting on a clock derived by dividing the system clock φs (= f /2) by 4. The counter is cleared on the rise of REF30X in record mode, and on the rise of PB-CTL in rewrite mode. REC-CTL match detection is carried out by comparing the counter value with each RCDR value.
Page 722: 26.13.10 Trapezoid Waveform Circuit
26.13.10 Trapezoid Waveform Circuit In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PB- CTL signal intact, but changes the duty cycle. In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5).
Page 723: 26.13.11 Note On Ctl Interrupt
26.13.11 Note on CTL Interrupt After a reset, the CTL circuit is in the VISS discrimination input mode. Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an interrupt request generated. If the interrupt request will be enabled, first clear the CTL interrupt request flag.
Page 724: 26.14.1 Overview
26.14 Frequency Dividers 26.14.1 Overview On-chip frequency dividers are provided for the pulse signal picked up from the control track during playback (the PB-CTL signal), and the pulse signal received from the capstan motor (CFG signal). The CTL frequency divider generates a CTL divided control signal (DVCTL) from the PB-CTL signal, for use in capstan phase control during high-speed search, for example.
Page 725 DVCTL Control Register (CTVC) Bit :    Initial value :    R/W : CTVC consists of the external input signal selection bits and the flags which show the CFG, HSW, and CTL levels. Note: It has an undetermined value by a reset or in stand-by mode. Bit 7...
Page 726 Bit 1    HSW Flag (HSW): Shows the level of the HSW signal selected by the VFF/NFF bit of the HSW mode register 2 (HSM2). Bit 1 Description HSW is at low level (Initial value) HSW is at high level Bit 0...
Page 727 Operation: During playback, control pulses recorded on the tape are picked up by the control head and input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier, reshaped, then input to the CTL frequency divider as the PB-CTL signal. This circuit is employed when the control pulse (PB-CTL signal) is used for phase control of the capstan motor.
Page 728 26.14.3 CFG Frequency Divider Block Diagram: Figure 26.65 shows a block diagram of the 7-bit CFG frequency divider and its mask timer. Internal bus CDVC CDIVR(7 bits) CDVC CDVC MCGin Edge Down counter (7 bits) select DVCFG ↑, ↑↓ Down counter (7 bits) DVCFG2 PB(ASM)→REC CDVC...
Page 729 Register Description: • Register configuration Table 26.23 shows the register configuration of the CFG frequency division circuit. Table 26.23 Register Configuration Name Abbrev. Size Initial Value Address DVCFG control register CDVC Byte H'60 H'D09A CFG frequency division CDIVR1 Byte H'80 H'D09B register 1 CFG frequency division...
Page 730 Bit 5    CFG Mask Status Bit (CMK): Indicates the status of the mask. It is initialized to 1 by a reset, or in stand-by or module stop mode. Bit 5 Description Indicates that the capstan mask timer has released masking Indicates that the capstan mask timer is currently masking (Initial value) Bit 4...
Page 731 Bits 1 and 0    CFG Mask Timer Clock Selection Bits (CPS1, CPS0): Selects the clock source for the CFG mask timer. (φs = fosc/2) Bit 1 Bit 0 CPS1 CPS0 Description φs/1024 (Initial value) φs/512 φs/256 φs/128 CFG Frequency Division Register 1 (CDIVR1) Bit : CDV16...
Page 732 CFG Frequency Division Register 2 (CDIVR2) Bit : CDV26 CDV25 CDV24 CDV23 CDV22 CDV21 CDV20 — Initial value : R/W : — CDIVR2 is an 8-bit write-only register to set the division value. If a read is attempted, an undetermined value is read out. Bit 7 is reserved. The frequency division value is written in the reload register and the down counter at the same time.
Page 733 Operation: • Frequency divider The CFG pulses output from the capstan motor are sent to internal circuitry as the CFG signal via the zero-cross type comparator. The CFG signal, shaped into a rectangular waveform by a reshaping circuit, is divided by the CFG frequency dividers, and used in servo control. The rising edge or both edges of the CFG signal can be selected for the frequency divider.
Page 734 CRF bit=1 CDIVR=00 CRF bit=0 CDIVR=00 CRF bit=0 CDIVR=01 CRF bit=0 CDIVR=02 Figure 26.66 CFG Frequency Division Waveforms Rev. 1.0, 02/00, page 728 of 1141...
Page 735 • Mask timer The capstan mask timer is a 6-bit reload timer that uses a prescaled clock as a clock source. The mask timer is used for masking DVCFG signal intended for controlling the capstan speed. The capstan mask timer prevents edge detection to be carried out for an unnecessarily long duration by masking the edge detection for a certain period.
Page 736 Figures 26.68 and 26.69 show examples of CFG mask timer operations. CFG (racing) Edge detect Capstan motor Mask interval Mask interval mask timer DVCFG Cleared by wiring 0 after reading 1 MCGin flag Figure 26.68 CFG Mask Timer Operation (When Capstan Motor is Racing) Edge detect Capstan motor Mask interval...
Page 737: 26.14.4 Dfg Noise Removal Circuit
26.14.4 DFG Noise Removal Circuit Block Diagram: Figure 26.70 shows the block diagram of the DFG noise removal circuit. Rising edge NCDFG detection Falling edge detection Delay circuit delay = 2φ Figure 26.70 DFG Noise Removal Circuit Register Description: Table 26.24 shows the register configuration of the DFG mask circuit. Table 26.24 Register Configuration Name Abbrev.
Page 738 Bit 0    DFG Edge Selection Bit (DRF): Selects the edge of the NCDFG signal used in the drum speed error detector. Bit 0 Description Selects the rising edge of NCDFG signal (Initial value) Selects the falling edge of NCDFG signal Operation The DFG noise removal circuit generates a signal (NCDFG signal) as a result of removing noise (signal fluctuation smaller than 2 φ) from the DFG signal.
Page 739: Sync Signal Detector
26.15 Sync Signal Detector 26.15.1 Overview This block performs detection of the horizontal sync signal (Hsync) and vertical sync signal (Vsync) from the composite sync signal (Csync), noise counting, and field detection. It detects the horizontal and vertical sync signals by setting threshold in the register and based on the servo clock (φs = fosc/2).
Page 740: 26.15.2 Block Diagram
26.15.2 Block Diagram Figure 26.72 shows the block diagram of the sync signal detector. Figure 26.72 Block Diagram of the Sync Signal Detector Rev. 1.0, 02/00, page 734 of 1141...
Page 741: Pin Configuration
26.15.3 Pin Configuration Table 26.25 shows the pin configuration of the sync signal detector. Table 26.25 Pin Configuration Name Abbrev. Function Composite sync signal input pin Csync Input Composite sync signal input 26.15.4 Register Configuration Table 26.26 shows the register configuration of the sync signal detector. Table 26.26 Register Configuration Name Abbrev.
Page 742: 26.15.5 Register Description
26.15.5 Register Description Vertical Sync Signal Threshold Register (VTR) Bit : — — VTR5 VTR4 VTR3 VTR2 VTR1 VTR0 Initial value : R/ W : — — VTR is an 8-bit write-only register that sets the threshold for the vertical sync signal when the signal is detected from the composite sync signal.
Page 743 Horizontal Sync Signal Threshold Register (HTR) Bit : HTR3 HTR2 HTR1 HTR0 — — — — Initial value : R/W : — — — — HTR is an 8-bit write-only register that sets the threshold for the horizontal sync signal when the signal is detected from the composite sync signal.
Page 744 Example The values set to detect the vertical and horizontal sync signals (SEPV, SEPH) from Csync are required to meet the following conditions. Assumed that the set values in VTHR register were VVTH and HVTH, (VVTH-1) × 2/φs > Hpulse (HVTH-2) ×...
Page 745 H Complement Start Time Setting Register (HRTR) Bit : HRTR7 HRTR6 HRTR5 HRTR4 HRTR3 HRTR2 HRTR1 HRTR0 Initial value : R/W : HRTR is an 8-bit write-only register that sets the timing to generate a complementary pulse if a pulse of the horizontal sync signal is missing. If a read is attempted, an undetermined value is read out.
Page 746 Noise Detection Window Setting Register (NWR) Bit : — — NWR5 NWR4 NWR3 NWR2 NWR1 NWR0 Initial value : R/W : — — NWR is an 8-bit write-only register that sets the period (window) when the drop-out of the horizontal sync signal pulse is detected and the noise is counted. Set the timing of the noise detection window in bits 5 to 0.
Page 747 Sync Signal Control Register (SYNCR) Bit : — — — — NIS/VD NOIS SYCT Initial value : — — — — R/W : R/(W)* Note: * Only 0 can be written SYNCR is an 8-bit register that controls the noise detection, field detection, polarity of the sync signal input, etc.
Page 748 Bit 1    Field Detection Flag (FLD): Indicates whether the field currently being scanned is even or odd. See figure 26.74. Bit 1 Description Odd field (Initial value) Even field Bit 0    Sync Signal Polarity Selection Bit (SYCT): Selects the polarity of the sync signal (Csync) to be input.
Page 749 Composite sync signal SEPV Noise detection window Field detection flag (FLD) Even field (a) Even field Composite sync signal SEPV Noise detection window Field detection flag (FLD) Odd field (b) Odd field Figure 26.74 Field Detection Rev. 1.0, 02/00, page 743 of 1141...
Page 750: 26.15.6 Noise Detection
26.15.6 Noise Detection If a pulse of the horizontal sync signal is missing, a complementary pulse is set at the timing set in HPWR and with the set pulse width. Set the noise detection window with HWR of about 1/4 of the horizontal sync signal, and the pulse with equal high and low periods will be obtained.
Page 751 A horizontal sync The pulse in the mask pulse is missing period is ignored SEPH H counter H'00 H'E8 H reload counter Don't mask immediately Mask Mask Mask Mask after period period period period complement. Noise mask for H counter OSCH Mask Mask...
Page 752 Noise Detection Operation: The noise detector considers an irregular pulse of the composite sync signal (Csync) and a chip of a horizontal sync signal pulse within a frame as noise. The noise counter takes counts of the irregular pulses during the high period of the noise detection window and the chips and drop-outs of the horizontal sync signal pulses during the low period.
Page 753: 26.15.7 Activation Of The Sync Signal Detector
26.15.7 Activation of the Sync Signal Detector After release of reset or transition from the power down mode to the active mode, the sync signal detector starts operation by a sync signal input after release of module stop. The pulse of the polarity specified by the SYCT bit of the sync signal control register (SYNCR) is input to the detector.
Page 754: Servo Interrupt
26.16 Servo Interrupt 26.16.1 Overview The interrupt exception processing of the servo module is started by one of ten factors, i.e. the drum speed error detector (×2), drum phase error detector, capstan speed error detector (×2), capstan phase error detector, HSW timing generator (×2), sync detector, and CTL circuit. For these interrupt factors, see each of their circuit sections of this manual.
Page 755 Bit 7    Drum Phase Error Detection Interrupt Enable Bit (IEDRM3) Bit 7 IEDRM3 Description Disables the request of the interrupt by IRRDRM3 (Initial value) Enables the request of the interrupt by IRRDRM3 Bit 6    Drum Speed Error Detection (Lock Detection) Interrupt Enable Bit (IEDRM2) Bit 6 IEDRM2 Description...
Page 756 Bit 2    Capstan Speed Error Detection (OVF, Latch) Interrupt Enable Bit (IECAP1) Bit 2 IECAP1 Description Disables the request of the interrupt by IRRCAP1 (Initial value) Enables the request of the interrupt by IRRCAP1 Bit 1    HSW Timing Generation (counter clear, capture) Interrupt Enable Bit (IEHSW2) Bit 1 IEHSW2 Description...
Page 757 Servo Interrupt Enable Register 2 (SIENR2) Bit : — — — — — — IESNC IECTL Initial value : R/W : — — — — — — SIENR2 is an 8-bit read/write register that enables or disables interrupts in the servo section. It is initialized to H'FC by a reset, stand-by or module stop.
Page 758 Servo Interrupt Request Register 1 (SIRQR1) Bit : IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. SIRQR1 is an 8-bit read/write register that indicates interrupt request in the servo section.
Page 759 Bit 4    Capstan Phase Error Detector Interrupt Request Bit (IRRCAP3) Bit 4 IRRCAP3 Description No interrupt request from the capstan phase error detector. (Initial value) Interrupt requested from the capstan phase error detector. Bit 3    Capstan Speed Error Detector (Lock Detection) Interrupt Request Bit (IRRCAP2) Bit 3 IRRCAP2 Description...
Page 760 Bit 0    HSW Timing Generator (OVW, Matching, STRIG) Interrupt Permission Bit (IRRHSW1) Bit 0 IRRHSW1 Description No interrupt request from the HSW timing generator (OVW, matching, STRIG). (Initial value) Interrupt requested from the HSW timing generator (OVW, matching, STRIG). Rev.
Page 761 Servo Interrupt Request Register 2 (SIRQR2) Bit : IRRSNC IRRCTL — — — — — — Initial value : — — — — — — R/(W)* R/(W)* R/W : Note: * Only 0 can be written to clear the flag. SIRQR2 is an 8-bit read/write register that indicates interrupt request in the servo section.
Page 762: Section 27 Sync Separator For Osd And Data Slicer
Section 27 Sync Separator for OSD and Data Slicer 27.1 Overview The sync separator separates the horizontal sync signal and vertical sync signal from the composite video signal input from the CVin2 terminal and sends the sync signals to the on screen display (OSD) module and data slicer.
Page 763: Features
27.1.1 Features • Horizontal sync signal separation: Stable separation is provided by the AFC, and complement and mask functions are available. • AFC reference clock frequency: 576 or 448 times the frequency of the horizontal sync signal can be selected. •...
Page 764 Figure 27.1 Sync Separator Block Diagram Rev. 1.0, 02/00, page 759 of 1141...
Page 765: Pin Configuration
27.1.3 Pin Configuration Table 27.1 shows the pin configuration of the sync separator. Table 27.1 Sync Separator Pin Configuration Name Abbrev. Function Sync signal Csync/Hsync Input/output Composite sync signal input/output or input/output horizontal sync signal input VLPF/Vsync Input Pin for connecting external LPF for vertical sync signal or input pin for vertical sync signal AFC oscillation...
Page 766: Register Description
27.2 Register Description 27.2.1 Sync Separation Input Mode Register (SEPIMR) Bit : CCMPV1 CCMPV0 COMPSL SYNCT VSEL DLPFON — FRQSEL Initial value : R/W : — The SEPIMR is an 8-bit read/write register for selecting the source signals for sync separation. In addition to the internal switches controlled by this register setting, the external circuits are used to select the sources of the Hsync and Vsync signals to be supplied to the digital H separation counter and the digital V separation counter, respectively.
Page 767 Table 27.3 Source Signals for Sync Separation CCMPSL VSEL Csync/ Input Vsync External External External External (Internal (Internal Hsync Source Detector SW5) SW6) Terminal CVin2 Vsync Output input Schmitt Csync Open Input Output Schmitt fixed to OVss Csync Vsync Input input Schmitt Csync...
Page 768 Bit 5    Csync Separation Comparator Input Select (CCMPSL): Controls internal switch SW5 to select whether to use the Csync separation comparator input or Csync Schmitt input. Writing 0 to this bit selects the Csync separation comparator input, and writing 1 selects the Csync Schmitt input.
Page 769 Bit 2    Digital LPF Control (DLPFON): Specifies the digital LPF function, which masks noise components of the Vsync signal in a weak field. The digital LPF logically ORs the Csync signal (Vsync signal) and the SEPH signal that is separated by the digital H separation counter, then inputs the ORed result to the digital V separation counter.
Page 770: Sync Separation Control Register (Sepcr)
27.2.2 Sync Separation Control Register (SEPCR) Bit : AFCVIE AFCVIF VCKSL VCMPON HCKSEL HHKON — Initial value : R/W : R/(W)* — Note: * Only 0 can be written to clear the flag. The SEPCR is an 8-bit read/write register for controlling the external Vsync interrupt, enabling or disabling the V complement function, selecting the clock source for the V complement and mask counter, selecting the clock source for the internal Csync generator, and indicating the field detected by the AFC.
Page 771 Bit 5    V Complement and Mask Counter Clock Source Select (VCKSL): Selects the clock source for the V complement and mask counter: double the frequency of the horizontal sync signal for the AFC (AFCH signal) or that for the H complement and mask counter (OSCH signal). When the text display mode is selected for the OSD and internally generated Hsync signal is selected as the reference Hsync signal for the AFC by setting the HSEL bit (bit 5) of the SEPACR, setting this VCKSL bit to 1 enables the external Vsync signal to be detected irrespectively of the text display...
Page 772 Bit 2    HHK Forcibly Turned On (HHKON): Forcibly operates the half Hsync killer (HHK) function when the H complement and mask counter interpolates complementary pulses three successive times. When the HVTHR is set within the range from 2.35 µs to 4.7 µs to remove equalizing pulses by using the digital H separation counter, the HHK function prevents Hsync- Vsync phase-difference errors during the V blanking period.
Page 773: Sync Separation Afc Control Register (Sepacr)
27.2.3 Sync Separation AFC Control Register (SEPACR) Bit : NDETIE NDETIF HSEL — — ARST — — Initial value : R/W : R/(W)* — — — — Note: * Only 0 can be written to clear the flag. The SEPACR is an 8-bit read/write register for controlling the AFC. The AFC generates a reference clock of 576 or 448 times the frequency of the horizontal sync signal.
Page 774 Bit 5    Reference Hsync Signal Select (HSEL): Selects the reference Hsync signal for the AFC: the external Hsync signal or the internally generated Hsync signal. When using the data slicer, select the external Hsync signal. When not using the data slicer but using the text display mode for the OSD, select the internally generated Hsync signal.
Page 775: Horizontal Sync Signal Threshold Register (Hvthr)
27.2.4 Horizontal Sync Signal Threshold Register (HVTHR) Bit : — — — HVTH4 HVTH3 HVTH2 HVTH1 HVTH0 Initial value : R/W : — — — The HVTHR is a 5-bit write-only register for specifying the threshold value for the digital H separation counter;...
Page 776 Csync HVTH Digital H separation counter SEPH About 3.2 µs to 2.0 µs Figure 27.4 HVTH Value and SEPH Generation Timing When Equalizing Pulses Are Not Detected The following shows examples of HVTHR settings. (HVTHR – 1) × (2/OSC) > 1.6 µs or 3.2 µs Condition: System clock OSC = 10 MHz 2/OSC = 5 MHz = 0.2 µs...
Page 777 Pulse lost Csync HVTH Digital H separation counter SEPH H complement and mask counter OSCH Comple- Comple- Hsync-Vsync ment ment phase-difference error Figure 27.5 Timing of Hsync-Vsync Phase-Difference Error When Equalizing Pulse Lost at Hsync Pulse Position Note: When 2.35-µs equalizing pulses are eliminated, the complement function operates for the eliminated period.
Page 778: Vertical Sync Signal Threshold Register (Vvthr)
Csync HVTH Digital H separation counter SEPH H complement and mask counter Forcible HHK Forcible HHK operation operation OSCH Comple- Comple- Comple- Comple- Comple- Comple- ment ment ment ment ment ment Figure 27.7 Timing of HHK Operation When Complementary Pulses Inserted Three Successive Times While HHKON = 1 27.2.5 Vertical Sync Signal Threshold Register (VVTHR) Bit :...
Page 779 The following shows an example of VVTHR settings. (VVTHR – 1) × (2/OSC) > (Hsync period / 2 – 4.7 µs) × 1.5 = 41 µs Condition: System clock OSC = 10 MHz 2/OSC = 5 MHz = 0.2 µs Example 1: To detect 41-µs pulses Vsync detection threshold value: 41 µs 41 µs / 0.2 µs = 205...
Page 780: Field Detection Window Register (Fwidr)
Csync VVTH Digital H separation counter SEPV 1/2 AFCH (V sampling clock) V complement and mask counter AFCV Figure 27.10 AFCV Generation Timing When V Complement Function Is Enabled (for NTSC) 27.2.6 Field Detection Window Register (FWIDR) Bit : — —...
Page 781 Bit 0    Field Detection Flag (FLD): Indicates the field determined by the status of the field detection window signal generated by the AFC when the external Vsync signal (AFCV signal) rises. This flag is invalid when the internally generated Hsync signal is selected as the AFC reference Hsync signal.
Page 782: H Complement And Mask Timing Register (Hcmmr)
27.2.7 H Complement and Mask Timing Register (HCMMR) Bit : HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 HC0 HM6 HM5 HM4 HM3 HM2 HM1 HM0 Initial value : R/W : The HCMMR is a 16-bit write-only register for specifying the timing (Th: Hsync frequency) for generating a complementary pulse when a pulse in the Hsync signal is lost, and the timing (Tm and Tm2) for clearing the HHK (masking period).
Page 783 Noise Pulse Csync lost HVTH Digital H separation counter SEPH H complement and mask counter Killer Killer Killer Killer (for counter reset) 5 µs HHK2 Killer Killer Killer Killer (for OSCH generation) OSCH Comple- mentary pulse Figure 27.12 Complement and Mask Timing of the H Complement and Mask Counter Bits 15 to 7...
Page 784: Noise Detection Counter (Ndetc)
Bits 6 to 0    HHK Period Setting (HM6 to HM0): Specify the timing for clearing the HHK (masking period) for the Hsync signal. The H complement and mask counter starts counting at a rising edge of the SEPH signal; the HHK period specified by these bits starts at this timing. This value is also used as the timing for resetting the noise detection window signal.
Page 785: Noise Detection Level Register (Ndetr)
27.2.9 Noise Detection Level Register (NDETR) Bit : Initial value : R/W : The NDETR is an 8-bit write-only register for specifying the noise detection level. The set value must be 1/4 of the actual noise detection level. The noise detection window signal is set to 1 at a falling edge of the OSCH signal, and reset to 0 after the time specified by the HHK period setting bits has passed.
Page 786: Data Slicer Detection Window Register (Ddetwr)
27.2.10 Data Slicer Detection Window Register (DDETWR) Bit : SRWDE1 SRWDE0 SRWDS1 SRWDS0 CRWDE1 CRWDE0 CRWDS1 CRWDS0 Initial value : R/W : The DDETWR is an 8-bit write-only register for specifying the timing of the clock run-in detection window signal and start bit detection window signal supplied to the data slicer. Figure 27.14 shows the timing of the signals.
Page 787 Bits 7 and 6    Start Bit Detection Window Signal Falling Timing Setting (SRWDE1 and SRWDE0): Specifies the falling timing (end timing) of the start bit detection window signal. Bit 1 Bit 0 SRWDE1 SRWDE0 Description The detection ends about 29.5 µs after the slicer start point (Initial value) The detection ends about 29.0 µs after the slicer start point The detection ends about 30.0 µs after the slicer start point...
Page 788: Internal Sync Frequency Register (Infrqr)
Bits 1 and 0    Clock Run-in Detection Window Signal Rising Timing Setting (CRWDS1 and CRWDS0): Specifies the rising timing (start timing) of the clock run-in detection window signal. Bit 1 Bit 0 CRWDS1 CRWDS0 Description The detection starts about 10.5 µs after the slicer start point (Initial value) The detection starts about 10.0 µs after the slicer start point The detection starts about 11.0 µs after the slicer start point...
Page 789: Operation
Bit 5    Hsync Frequency Selection (HFS): Selects the Hsync frequency. Here, fsc indicates the color subcarrier signal frequency in each TV format. Note that this setting is ignored when the HCKSEL bit (bit 3) of the SEPCR is set to 1 to select the AFC clock as the internal Csync generator clock source and when the FSCIN bit (bit 12) of the DFORM in the OSD is set to 1 to select the 2fsc clock.
Page 790 External circuit Inside LSI CCMPSL Csync separation comparator CVin2 – CVin2 Hsync Digital H Reference separation Sync tip SEPH voltage switch counter clamp CCMPV0, 1 Internal Register control Csync External I/O switch DLPFON External Csync/Hsync Digital V SEPV separation switch Polarity counter switch...
Page 791 (b) Using the Csync Schmitt Circuit The Hsync component is processed in the same way as described in (a), but the Vsync component is processed differently; the Csync/Hsync terminal is left open and the separated Vsync component is input through the Csync Schmitt circuit to the digital V separation counter.
Page 792 (2) Inputting the Csync Signal as the Source When the Csync signal is selected as the source, the Vsync component can be processed in two methods: using the Vsync Schmitt circuit or using the Csync Schmitt circuit. (a) Using the Vsync Schmitt Circuit The Csync signal having the polarity selected by the SYNCT bit (bit 4) of the SEPIMR is input to the Csync/Hsync terminal.
Page 793 (b) Using the Csync Schmitt Circuit The Hsync component is processed in the same way as described in (a), but the Vsync component is processed differently; the Vsync component is input through the Csync Schmitt circuit to the digital V separation counter. Figure 27.18 shows this method. External circuit Inside LSI CCMPSL...
Page 794 (3) Inputting the Hsync and Vsync Signals Separately as Sources The Hsync signal having the polarity selected by the SYNCT bit (bit 4) of the SEPIMR is input to the Csync/Hsync terminal, and is input through the Csync Schmitt circuit to the digital H separation counter;...
Page 795: Vsync Separation
27.3.2 Vsync Separation The Hsync separator separates the Vsync signal from the Csync signal by using the digital V separation counter, which is an 8-bit up-/down-counter, and the VVTHR register, which holds the threshold value. The digital V separation counter increments the count when the Csync signal is high, and decrements the count when the Csync is low.
Page 796: Hsync Separation
27.3.3 Hsync Separation The Hsync separator separates the Hsync signal from the Csync signal by using the digital H separation counter, which is a 5-bit up-/down-counter, and the HVTHR register, which holds the threshold value. The digital H separation counter increments the count when the Csync signal is high, and decrements the count when the Csync is low.
Page 797: Field Detection
27.3.4 Field Detection The sync separator detects whether the current field is an even field or an odd field from the 1/2H phase difference between the Hsync and Vsync by using the AFCV signal generated by the V complement and mask counter and the field detection window signal generated by the AFC. The timing of the field detection window signal can be adjusted by the FWIDR setting so that it is suitable for comparison with the AFCV signal.
Page 798: Automatic Frequency Controller (Afc)
27.3.6 Automatic Frequency Controller (AFC) The AFC averages the Hsync signal fluctuation of the video signal. Figure 27.20 shows the AFC configuration. The AFC generates a reference clock having 576 or 448 times the frequency (576 × fh or 448 × fh) of the Hsync signal. From this clock, several clocks are generated, such as the horizontal sync signal (AFCH signal), clock run-in detection window signal, start bit detection window signal, V complement and mask counter clock when the V complement function is selected, and the field detection window signal.
Page 799 (1) AFC Oscillator The AFCosc terminal, which is the oscillation signal terminal of the voltage controlled oscillator (VCO), oscillates at 576 times the frequency (576 × fh) of the Hsync signal when the Hsync signal is input at a certain phase and frequency. The difference in phase or frequency is detected between the reference Hsync signal and the Hsync signal (AFCH signal) obtained by dividing the 576 ×...
Page 800 Table 27.4 Reference Hsync Signal for AFC V Comple- Reference ment and Hsync Mask Data Slicer Field Signal Operation Operation Detection Counter HCKSEL HSEL VCKSL External Operates/ Super- Operates Twice the Hsync Stops imposed frequency of signal mode the AFCH Internally Stops Text...
Page 801 AFCosc 12µH 12pF 470Ω AFCpc 0.01µF Reset, active, or sleep 1/2OVcc AFCLPF Phase error signal 2.4kΩ 4.7µF 0.01µF Note: Reference values are shown. Figure 27.22 Circuit Example for a 448 × × × × fh Reference Clock Rev. 1.0, 02/00, page 796 of 1141...
Page 802: Module Stop Control Register (Mstpcr)
27.3.7 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR is a 16-bit read/write register for controlling the module stop mode. Writing 0 to the MSTP9 bit starts the sync separator;...
Page 803: Section 28 Data Slicer
Section 28 Data Slicer 28.1 Overview The data slicer extracts signals for closed caption signal in the U.S. This function can be used to extract caption data superimposed on the vertical blanking interval of TV video signals. A high-performance internal sync separator enables reliable caption data extraction. The data slicer will not operate when 448 times the horizontal sync frequency is selected for the AFC reference clock frequency.
Page 804: Block Diagram
28.1.2 Block Diagram Figure 28.1 shows the block diagram of the data slicer. Sync separator Sync signal Line H complement generation counter and mask Dot clock Reference clock Field determination circuit Line counting Field Slice line specification circuit Clock run-in CVin2 Clock run-in –...
Page 805: Pin Configuration
28.1.3 Pin Configuration Table 28.1 shows the pin configuration for the data slicer. Table 28.1 Data Slicer Pin Configuration Block Name Abbrev. Function Sync Sync signal Csync/Hsync Input/output Composite sync signal input/output separator input/output or horizontal sync signal input VLPF/Vsync Input Pin for connecting external LPF for vertical sync signal or input pin for...
Page 806: Register Configuration
28.1.4 Register Configuration Table 28.2 shows the data slicer registers. Table 28.2 Register Configuration Name Abbrev. Size Initial Value Address* Slice even-field mode register SEVFD R/(W)* Word/byte H'2000 H'D220 Slice odd-field mode register SODFD R/(W)* Word/byte H'2000 H'D222 Slice line setting register 1 SLINE1 Word/byte H'20...
Page 807: Register Description
28.2 Register Description 28.2.1 Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD) (1) Slice even-field mode register Bit: EVNIE STBE0 EVNIF — STBE4 STBE3 STBE2 STBE1 Initial value: R/(W)* — R/W: Bit: SLVLE2 SLVLE1 SLVLE0 DLYE4 DLYE3 DLYE2 DLYE1 DLYE0 Initial value: R/W: (2) Slice odd-field mode register...
Page 808 Bit 15    Even- (Odd-) Field Slice Completion Interrupt Enable Flag (EVNIE, ODDIE): Enables or disables the generation of even- (odd-) field slice completion interrupts. Bit 15 EVNIE ODDIE Description Disables even- (odd-) field slice completion interrupt (Initial value) Enables even- (odd-) field slice completion interrupt Bit 14...
Page 809 Clock run-in Start S1 S2 S3 C.video Data slicer base point Clock run-in detection window signal Approx. 23.5 µs Set by STB Start bit detectable Start bit detection period window signal Te = Approx. 29.5 µs TS = 23.5 µs + µs ×...
Page 810 Bits 4 to 0    Data Sampling Delay Time Setting Bits (DLYE4 to DLYE0) (DLYO4 to DLYO0): Set the even (odd) field data sampling clock delay time. Figure 28.3 explains the data sampling clock. The data sampling clock is a clock with period 32×fh, used for slicing 16-bit closed caption data. The data sampling clock is generated after the rising edge of the start bit is detected and the time set by the DLY bit is passed.
Page 811: Slice Line Setting Registers 1 To 4 (Sline1 To Sline4)
28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4) Bit: SENBLn SFLDn — SLINEn4 SLINEn3 SLINEn2 SLINEn1 SLINEn0 Initial value: R/W: — The slice line setting registers 1 to 4 (SLINE1 to SLINE4) specify slice fields and lines. Up to four slice lines can be specified;...
Page 812: Slice Detection Registers 1 To 4 (Sdtct1 To Sdtct4)
Bit 5    Reserved: Cannot be modified and is always read as 1. Bits 4 to 0    Slice Line Setting Bits (SLINE4 to SLINE0): Specify the data slice line. Slice lines up to H'1F (31) can be specified. Figure 28.4 explains the line count.
Page 813 Slice line setting register n Slice detection register n Data slice result information Line m for line m Figure 28.5 Relationship between Slice Line Set t i ng R egi s t er and Sl i ce D et ect i on R egi s t er SDTCT is an 8-bit read-only register.
Page 814 Start C.video Data slicer base point Start bit detection starting position Start bit detection end position Data sampling clock Delay Figure 28.6 Data Sampling Clock When Start Bit is not Detected Bit 5    Data End Detection Flag (ENDFn n=1 to 4): Shows whether or not slice data is input at the 18th sampling clock pulse.
Page 815: Slice Data Registers 1 To 4 (Sdata1 To Sdata4)
28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4) Bit: Initial value: R/W: *: Unefined The slice data registers 1 to 4 (SDATA1 to SDATA4) are registers in which the slice results are stored. The data is stored in LSB-first fashion, in order from the LSB side near the start bit. Figure 28.7 shows how to store the slice data.
Page 816: Module Stop Control Register (Mstpcr)
When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the SDATA register values are indeterminate. 28.2.5 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit: MSTP MSTP MSTP MSTP MSTP...
Page 817: Monitor Output Setting Register (Dout)
28.2.6 Monitor Output Setting Register (DOUT) Bit: — RGBC YCOC DOBC DSEL CRSEL — — Initial value: R/W: — — — The internal signals used by the data slicer can be monitored through the R, G, B, YCO, and YBO pins.
Page 818: Operation
28.3 Operation 28.3.1 Slice Line Specification Up to four slice lines can be specified using the slice line setting registers 1 to 4. For information on field discrimination, refer to section 27.2.6, Field Detection Window Register (FWIDR). After completion of data slicing for all lines specified by registers, a slice completion interrupt is output;...
Page 819 The data slicer initialization and operation for one specification example are shown in figure 28.9. Contents of slice line setting registers Slice Line Setting Register Register No. Enable Field Line Even Line c Line b Even d > c Line d b >...
Page 820 Operation for data slicer resetting for a second specification is shown in figure 28.10. Contents of slice line setting registers Contents of slice line setting registers Slice Line Setting Register Slice Line Setting Register Register No. Register No. Enable Field Line Enable Field...
Page 821: Slice Sequence
28.3.2 Slice Sequence Figure 28.11 shows the slice sequence. • Line detection The specified slice line and field match the line count and detected field Set the clock run-in count • Clock run-in detection Count the number of clock run-in pulses in clock run-in period Set clock run-in detection flag (Enable the clock run-in detection)
Page 822: Section 29 On-Screen Display (Osd)
Section 29 On-Screen Display (OSD) 29.1 Overview OSD (on-screen display) is a function for superimposing arbitrary characters or display patterns on a TV image signal. The display screen consists of up to 32 characters × 12 rows; a single character consists of 12 dots ×...
Page 823 • Background colors: Eight hues* Background brightness, chroma saturation: Four brightness levels, two chroma levels • Character colors: Text display: Eight hues (character units)* Superimposed display: White Character brightness, chroma saturation: Four brightness levels, two chroma levels • Cursor: Character background colored during text display (character units) •...
Page 824: Block Diagram
29.1.2 Block Diagram A block diagram of the OSD appears in figure 29.1. Sync separator clock 4/2fsc TV format Horizontal Vertical display display position position control control Character data ROM Display data RAM Shift register Border control Button control 4/2fsc in Color burst Display control 4/2fsc...
Page 825: Pin Configuration
29.1.3 Pin Configuration The OSD pin configuration is shown in table 29.1. Even when not using the data slicer, the composite video signal should be input to Cvin2 in order to perform sync separation from the composite video signal. Table 29.1 OSD Pin Configuration Block Name Abbrev.
Page 826: Register Configuration
Block Name Abbrev. Function Data Composite Cvin2 Input Composite video signal input (2 Vpp, slicer video signal with a sync tip clamp circuit) 29.1.4 Register Configuration Table 29.2 shows the OSD registers. Table 29.2 Register Configuration Initial Name Abbrev. Size Value Address* Character data ROM...
Page 827: Tv Formats And Display Modes
29.1.5 TV Formats and Display Modes Table 29.3 indicates support for different TV formats in each display mode. Operation is not guaranteed if a frequency resulting from division by 4 or 2 from the 4fsc/2fsc input pin is not one of those listed in table 29.3.
Page 828: Character Configuration
29.2.2 Character Configuration Displayed characters and patterns consist of 12 dots × 18 lines per character. There are notes on creation of OSD fonts. For details, refer to section 29.8, Notes on OSD Font Creation. An example of a character configuration appears in figure 29.2. An example of an enlarged character appears in figure 29.3.
Page 829: On-Screen Display Configuration
24 dots 12 dots 36 lines 18 lines (1) Standard character size (2) Enlarged character size Figure 29.3 Enlarged Character Example 29.2.3 On-Screen Display Configuration The on-screen display area consists of 12 horizontal rows each containing up to 32 characters. The correspondence between display data RAM and the screen display is indicated in figure 29.4.
Page 830: Settings In Character Units
32nd character character character character character Row 1 D800 D802 D804 D806 D83E D840 D842 D844 D846 D87E Row 2 Row 11 DA80 DA82 DA84 DA86 DABE Row 12 DAC0 DAC2 DAC4 DAC6 DAFE Note: D800 to DAFF indicate the lower 16 bits of addresses in the on-screen display RAM. Figure 29.4 Correspondence between Display Data RAM and On-Screen Display 29.3 Settings in Character Units...
Page 831: Halftones/Cursors
Table 29.4 Correspondence between Character Color Code Settings and Color Output Signals Display Data RAM Settings* R, G, or B port White Yellow Magenta Cyan Green Blue Black output π/2 π C.Video output White Same 3π/4 3π/2 7π/4 Black (NTSC) phase C.Video output White...
Page 832: Blinking
12 dots 12 dots 18 lines 18 lines Halftone Background Character Cursor Background Character (1) Halftone display (2) Cursor display (Supported in superimposed mode) (Supported in text display mode) Figure 29.5 Halftone and Cursor Display Examples 29.3.4 Blinking Blinking is a function in which displayed characters are displayed intermittently. By specifying blinking in display data RAM, text can be made to blink in character units.
Page 833: Button Display
29.3.5 Button Display Button display is a function in which a frame is drawn around a character string; buttons can be set in character units in display data RAM. There are two types of button: one type of button appears to be raised or floating, and the other type appears to be lowered or sunken.
Page 834: Character Data Rom (Osdrom)
BPTn BON1 0/1* BON0 0/1* BPTn BON1 BON0 Note: * Do not set (start) or (end). Figure 29.6 Button Display Examples 29.3.6 Character Data ROM (OSDROM) The character data ROM (OSDROM) contains 384 character types, each consisting of 12 dots by 18 lines.
Page 835 Memory map 000000 Line 1, H' F 040040 bits 11 to 8 Line 1, 040041 bits 7 to 0 040000 Bit data for character Line 2, 040042 code H'000 H' F bits 11 to 8 CPU program (blank character display)* 04003F Line 2, 040043...
Page 836: Display Data Ram (Osdram)
12 dots Line number Data F000 11109 8 7 6 5 4 3 2 1 F000 F3FC F3FC F300 F300 Line F300 18 dots F300 F3F0 F3F0 32 words F300 F300 F300 F300 F300 F300 Unused area F000 F000 FFFF FFFF 16 bits Figure 29.8 OSDROM Data Configuration (for the letter “F”)
Page 837 The OSD display changes when the data written to master RAM is transferred to the slave RAM. Data is transferred from the master RAM to the slave RAM by setting the LDREQ bit in the OSD format register to 1. At this time, when the DTMV bit is 0, transfer is performed at the moment the LDREQ bit is set to 1;...
Page 838 Bit 14    Halftone/Cursor Display Specification Bit (HT/CR): Turns halftone/cursor display on and off in character units. The superimposed/text display mode switching bit of the screen control register is used for switching between halftone and cursor display. In digital outputs (R, G, and B), when the RGBC bit of the digital output specification register is set to 1 in either superimposed or text display mode to select output of display data for all of characters/borders/cursor/background/button display, the cursor color data specified by the cursor color specification bit of the row register is output.
Page 839 Bits 13 and 12    Button Specification Bits (BON1 and BON0): Set buttons in character units in conjunction with the BPTNn bit of the row register. To create a button with three or more characters, no-button display characters or button display (one character) must be specified between a button display (start) character and a button display (end) character.
Page 840 Bits 11 to 9    Character Color Specification Bits (CR, CG, and CB): Specify character colors in character units. In superimposed mode, the only character color is white, and register settings are invalid. For digital outputs (R, G, and B), character color data specified by the character color specification bits for both superimposed and text display modes is output.
Page 841: Settings In Row Units
29.4 Settings in Row Units The following items can be set in row units by using the row registers. 29.4.1 Button Patterns Characters can be set freely by writing, to display data RAM, the character data ROM address (character code) at which the character to be displayed is stored. For information on character data ROM and display data RAM, refer to section 29.3.6, Character Data ROM (OSDROM), and section 29.3.7, Display Data RAM (OSDRAM).
Page 842 Table 29.5 Correspondence between Cursor Color Code Settings and Color Output Signals Register Settings* R, G, or B port White Yellow Magenta Cyan Green Blue Black output π/2 π C.Video output White Same 3π/4 3π/2 7π/4 Black (NTSC) phase C.Video output White ±0 ±3π/4...
Page 843: Row Registers (Clinen, N = Rows 1 To 12)
100IRE Cursor region 0IRE –40IRE (a) No halftone 100IRE 100IRE Cursor region Cursor region 0IRE 0IRE 50% halftone 30% halftone –40IRE –40IRE (b) 50% halftone (c) 30% halftone Figure 29.9 Halftone Level Examples (C.Video) 29.4.5 Row Registers (CLINEn, n = rows 1 to 12) Bit: BPTNn CLUn1...
Page 844 All of the row registers 1 to 12 have the same specifiable format. When the OSD display update timing control bit (DTMV) is 1, the OSD display is updated to the row register settings in synchronous with the Vsync signal (OSDV). Bit 7...
Page 845 Bits 5 and 4    Character Brightness Specification Bits (CLUn1 and CLUn0, n = 1 to 12): Set the character brightness. The character brightness differs with the character color. In superimposed mode, white is the only character color. This setting has no effect on digital outputs (YCO, YBO, R, G, and B).
Page 846 Bits 3 to 1    Cursor Color Specification Bits (KRn, KGn, and KBn, n = 1 to 12): Set the cursor color in row units. C.Video output in superimposed mode uses halftone display, so that cursor color specifications are invalid. •...
Page 847 Bit 0    Cursor Brightness/Halftone Level Specification Bit (KLUn, n = 1 to 12): Sets the cursor brightness/halftone level in row units. Cursor brightness differs for different cursor colors. This setting has no effect on digital outputs (YCO, YBO, R, G, and B). •...
Page 848: Settings In Screen Units
29.5 Settings in Screen Units The following items can be set in screen units by using vertical display position register, horizontal display position register, and screen control register. 29.5.1 Display Positions (1) Vertical Display Start Position The vertical display start position can be set in single scanning line units using the vertical position specification bits of the vertical display position register.
Page 849: Turning The Osd Display On And Off
Note the following when choosing display position settings. • Settings should be chosen such that the display does not overlap with the color burst. • When the display protrudes outside the screen, characters in the protruding region should be blank characters (character code H'000). The base point for the horizontal display start position is shown in figure 29.11.
Page 850: Borders
29.5.5 Borders Borders on the periphery of characters can be set using the border specification bit of the screen control register. For an example of border display, see figure 29.2, Character Configuration Examples. The border color can be set in screen units using the border color specification bit of the screen control register.
Page 851: Display Position Registers (Hpos And Vpos)
29.5.8 Display Position Registers (HPOS and VPOS) The HPOS and VPOS include the horizontal display position register and the vertical display position register. (1) Horizontal Display Position Register (HPOS) Bit: Initial value: R/W: The horizontal display position register is used to set the horizontal display start position for characters.
Page 852 Bits 15 to 12    Reserved: Cannot be modified and are always read as 1. Bits 11 to 9    Vertical Row Interval Specification Bits (VSPC2 to VSPC0): Set the row interval in the vertical direction. They can be set in single scanning line units. Bit 11 Bit 10 Bit 9...
Page 853: Screen Control Register (Dcntl)
29.5.9 Screen Control Register (DCNTL) Bit: CDSPON DISPM LACEM BLKS OSDON — EDGE EDGC Initial value: — Bit: BLU1 BLU0 CAMP KAMP BAMP Initial value: The DCNTL is a 16-bit read/write register used to switch between superimposed and text display modes, set the background and color for text display mode in screen units, and turn OSD display on and off.
Page 854 Bit 13    Interlaced/Noninterlaced Display Select Bit (LACEM): Selects interlaced or noninterlaced text display mode. When noninterlaced text display is selected, the internally generated Hsync and Vsync frequency can be modified. For details, refer to section 27.2.11, Internal Sync Frequency Register (INFRQR). Bit 13 LACEM Description...
Page 855 Bit 10    Reserved: Cannot be modified and is always read as 0. When 1 is written to this bit, correct operation is not guaranteed. Bit 9    Border Specification Bit (EDGE): Sets the border for characters for the entire screen. Bit 9 EDGE Description...
Page 856 Bits 7 to 5    Background Color Specification Bits (BR, BG, and BB): Used to select the background color in text display mode. Background color specifications for C.Video output are invalid in superimposed mode. • Background Colors in Text Display Mode Background Color C.Video Output Bit 7...
Page 857 Bits 4 and 3    Background Brightness Select Bits (BLU1 and BLU0): Select the background brightness in text display mode. These settings have no effect on digital outputs (YCO, YBO, R, G, and B). Bit 4 Bit 3 BUL1 BUL0 Background Brightness...
Page 858: Other Settings
29.6 Other Settings 29.6.1 TV Format The OSD supports M/NTSC, 4.43-NTSC, M/PAL, N/PAL, B, G, H/PAL, I/PAL, D, K/PAL, and SECAM formats. See table 29.3, TV Formats and Display Modes. 29.6.2 Display Data RAM Control The OSD display data RAM consists of master RAM and slave RAM. The master RAM can be read and written by the CPU;...
Page 859: Osd Format Register (Dform)
29.6.6 OSD Format Register (DFORM) Bit: TVM2 TVM1 TMV0 FSCIN FSCEXT — OSDVE OSDVF Initial value: R/W: R/(W)* Bit: — — — — — DTMV LDREQ VACS Initial value: R/W: — — — — — R/(W)* Note: * Only 0 can be written to clear the flag. The DFORM is used to set the TV format and control display data RAM.
Page 860 Bits 15 to 13    TV Format Select Bits (TVM2 to 0): Select the TV format. The specified clock signal should always be input. Bit 15 Bit 14 Bit 13 Bit 12 Description TVM2 TVM1 TVM0 FSCIN TV Format 4fsc (MHz) 2fsc (MHz) M/NTSC...
Page 861 Bit 11    4/2fsc External Input Select Bit (FSCEXT): Selects 4fsc or 2fsc input. Bit 11 FSCEXT Description 4/2fsc oscillator uses a crystal oscillator (Initial value) 4/2fsc uses a dedicated amplifier circuit for external clock signal input Bit 10    Reserved: Always read as 0. When 1 is written to this bit, correct operation is not guaranteed.
Page 862 Bit 2    OSD Display Update Timing Control Bit (DTMV): Selects the timing for transfer of data from master RAM to slave RAM and for OSD display update by register overwriting. Bit 2 DTMV Description After the LDREQ bit is written to 1, data is transferred from master RAM to slave RAM regardless of the Vsync signal (OSDV).
Page 863: Digital Output
Bit 0    Master-Slave RAM Transfer State Bit (VACS): Is set to 1 if the CPU accesses OSDRAM during transfer of data from master RAM to slave RAM; the access is invalid. This bit is not cleared automatically, and so should be cleared by writing 0. Bit 0 VACS Description...
Page 864 Output Example 1 Character color: Yellow (CR = 1, CG = 1, CB = 0) Cursor color: Cyan (KR = 0, KG = 1, KB = 1) Background color: Green (BR = 0, BG = 1, BB = 0) Border: None (EDGE = 0) Button: Displayed (pattern 1)
Page 865 Output Example 2 Character color: Yellow (CR = 1, CG = 1, CB = 0) Cursor color: None (HT/CR = 0) Background color: Green (BR = 0, BG = 1, BB = 0) Border: Black (EDGE = 1, EDGC = 0) Button: None DOUT...
Page 866: Yco And Ybo Outputs
29.7.2 YCO and YBO Outputs YCO output consists of character and border data in dot units. Either of two YCO output methods can be selected by the YCO digital output specification bit: output of characters only, or combined output of character and border data. The digital output blink control bit can be used to select blinking for YCO output.
Page 867: Digital Output Specification Register (Dout)
Display block Horizontal display position 1 2 3 4 5 6 7 ................Row 1 Character display position Blank character Figure 29.15 YBO Output Example 29.7.3 Digital Output Specification Register (DOUT) Bit: — RGBC YCOC DOBC DSEL CRSEL — —...
Page 868 Bit 5    YCO Digital Output Specification Bit (YCOC): Specifies the YCO digital output format. This bit must be reset to 0 when bordering is not performed, and must be set to 1 when bordering is performed. Bit 5 YCOC Description Character output is specified...
Page 869: Module Stop Control Register (Mtstpcr)
Bit 2    Monitor Signal Switching Bit (CRSEL): Selects whether a clock run-in detection window signal or a start bit detection window signal is output. This bit setting is valid when DSEL is 1, so that pins are used as data slicer internal monitor signal outputs. Bit 2 CRSEL Description...
Page 870 Bit 0    Module Stop (MSTP0): Specifies the module stop mode for the OSD module. Bit 0 MSTP0 Description Clears the module stop mode for the OSD module Specifies the module stop mode for the OSD module (Initial value) Rev.
Page 871: Notes On Osd Font Creation
29.8 Notes on OSD Font Creation 29.8.1 Note 1 on Font Creation (Font Width) In OSD display, vertical and diagonal lines in fonts that are one dot wide may appear to be narrow due to a shift of 0.5H. Display fonts should be created with liberal thicknesses. 29.8.2 Note 2 on Font Creation (Borders) Borders extend beyond the character display frame in the X-direction, but no borders extend...
Page 872 Blank display 12 dots 18 dots Characters Borders Figure 29.17 Border Neighboring a Blank Character (Example) 12 dots 12 dots (a) 1st character (b) 32nd character Characters Borders Figure 29.18 Examples of Characters at the Starting and Ending Positions in a Row Rev.
Page 873: Note 3 On Font Creation (Blinking)
29.8.3 Note 3 on Font Creation (Blinking) Blinking involves intermittent display within a specified display frame only. When blinking is necessary, font data should not be set to the first or twelfth dots in the X-direction. Figure 29.19 shows an example of blinking for characters with borders extending beyond the display frame.
Page 874: Note 4 On Font Creation (Buttons)
29.8.4 Note 4 on Font Creation (Buttons) Buttons replace the outermost perimeter of the character display area with a button pattern. It should be remembered that the button pattern display takes priority over display of the font and border, if any. Figure 29.20 shows an example of button pattern display that takes priority over font and border.
Page 875: Osd Oscillator, Afc, And Dot Clock
29.9 OSD Oscillator, AFC, and Dot Clock In order to use the OSD, sync signals and a 4/2fsc clock signal are required. 29.9.1 Sync Signals The sync signal for text display mode is a signal created from a 4/2fsc clock or an AFC reference clock.
Page 876: 4/2Fsc
Table 29.6 Dot Clock Cycle Dot Clock Cycle Reference Clock: Reference Clock: 576 × × × × fh 448 × × × × fh TV Format M/NTSC, 4.43-NTSC, M/PAL, N/PAL 110 ns (9.06 MHz) 142 ns (7.06 MHz) B, G, H/PAL, I/PAL, D, K/PAL, SECAM 111 ns (9.00 MHz) 143 ns (7.00 MHz) 29.9.4...
Page 877 External clock select 4/2fsc in Power-down External clock mode controller Duty: 47 to 53% (OPEN) Note: C = 1000 pF typ When the external clock amplitude is 1 Vp-p or larger, connect a resistor in series with capacitor C. Figure 29.22 Example of Input of a 4/2fsc External Clock 2.
Page 878: Osd Operation In Cpu Operation Modes
29.10 OSD Operation in CPU Operation Modes Table 29.8 shows the OSD CVout pin status for different CPU operating modes. During a transition to power-down mode, registers are initialized, and so register settings must be restored on return to active mode. Table 29.8 OSD Operation for Different CPU Operating Modes Operating Mode Module Stop Bit...
Page 879: Character Data Rom (Osdrom) Access By Cpu
29.11 Character Data ROM (OSDROM) Access by CPU The character data ROM can be accessed by the CPU as part of user ROM. Before accessing the character data ROM by the CPU, clear the OSDON bit in the screen control register to 0 to stop OSD display, then set the OSROME bit in the serial timer register to 1.
Page 880: Section 30 Electrical Characteristics
Section 30 Electrical Characteristics 30.1 Absolute Maximum Ratings Table 30.1 lists the absolute maximum ratings. Table 30.1 Absolute Maximum Ratings Item Symbol Value Unit −0.3 to +7.0 Power supply voltage −0.3 to Vcc+0.3 Input voltage (ports other than port 0) −0.3 to AVcc+0.3 Input voltage (port 0) −0.3 to +7.0...
Page 881: Electrical Characteristics Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2 Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 30.2.1 DC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 Table 30.2 DC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V* , Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Test...
Page 882 Values Test Item Symbol Applicable Pins Conditions Unit Notes  Input low Vcc=2.5 V to –0.3 0.1 Vcc voltage 5.5 V −0.3  5(6, FWE, IC, 0.2 Vcc IRQ0 to IRQ5 −0.3  Vcc=2.5 V to 0.1 Vcc 5.5 V −0.3 ...
Page 883 Values Test Item Symbol Applicable Pins Conditions Unit Notes −I   Output SO1, SCK1, PWM1, =1.0mA Vcc–1.0 high PWM2, PWM3, −I   =0.5mA Vcc– Refer- voltage PWM4, PWM14, ence BUZZ, TMO, TMOW, value FTOA, FTOB, PPG0 to −I ...
Page 884 Values Test Item Symbol Applicable Pins Conditions Unit Notes I    µA Input MD0, FWE Vin=0.5 to /output Vcc–0.5V leakage   5(6, ,543 to ,548, ,& Vin=0.5 to current Vcc–0.5V   SCK1, SI1, SDA0, Vin=0.5 to SCL0, SDA1, SCL1, Vcc–0.5V FTIA, FTIB, FTIC, FTID,...
Page 885 Values Applicable Test Item Symbol Pins Conditions Unit Notes   Active Vcc=5V, mode =10 MHz, current High-speed dissipa- mode tion (CPU   Vcc=5V, Reference value operating) =10 MHz, Medium-speed mode (1/64)  Active Vcc=5V, — mode =10 MHz current dissipa- tion...
Page 886 Values Test Item Symbol Applicable Pins Conditions Unit Notes   µA Vcc=2.5V, Watch WATCH 32kHz mode With crystal current oscillator dissipa-   µA Vcc=5.0V, Reference tion 32kHz value* With crystal oscillator   µA X1=V , 32kHz Standby STBY Without crystal mode...
Page 887 Table 30.4 Bus Drive Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C) Applicable pin: SCL0, SCL1, SDA0, SDA1 Values Test Item Symbol Applicable Pins Unit Notes...
Page 888: Allowable Output Currents Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2.2 Allowable Output Currents of HD6432199, HD6432198, HD6432197, and HD6432196 The specifications for the digital pins are shown below. Table 30.5 Allowable Output Currents of HD6432199, HD6432198, HD6432197, and HD6432196 (Conditions: Vcc = 2.5 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C) Item Symbol Value...
Page 889: Ac Characteristics Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2.3 AC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 Table 30.6 AC Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 − − − − Preliminary − − − − (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable...
Page 890 Values Applicable Test Item Symbol Pins Conditions Unit Figure   5(6 pin low level Vcc = 2.5 V to Figure width 5.5 V 30.4   ,543 to ,548, Input pin high level Vcc = 2.5 V to Figure ,&, $'75*, width 5.5 V...
Page 891 4.0V OSC1 φ (Internal) DEXT Note: The t includes the pin Low level width 20 t DEXT Figure 30.3 External Clock Stabilization Delay Timing Figure 30.4 Reset Input Timing TMBI, FTIA, FTIB, FTIC, FTID, RPTRIG Figure 30.5 Input Timing Rev. 1.0, 02/00, page 888 of 1141...
Page 892: Serial Interface Timing Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2.4 Serial Interface Timing of HD6432199, HD6432198, HD6432197, and HD6432196 Table 30.7 Serial Interface Timing of HD6432199, HD6432198, HD6432197, and − − − − Preliminary − − − − HD6432196 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable...
Page 893 SCK1 Figure 30.7 SCI I/O Timing/Clock Synchronization Mode 2.4 kΩ LSI output pin 12 kΩ 30 pF Timing reference level : 2.0 V : 0.8 V Figure 30.8 Output Load Conditions Rev. 1.0, 02/00, page 890 of 1141...
Page 894 Table 30.8 I C Bus Interface Timing of HD6432199, HD6432198, HD6432197, and HD6432196 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Test Item Symbol Conditions Min Unit Figure ...
Page 895 SCLH STOS STAH STAS SCLL SDAS SDAH Note: S, P and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions Figure 30.9 I C Bus Interface I/O Timing Rev. 1.0, 02/00, page 892 of 1141...
Page 896: A/D Converter Characteristics Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2.5 A/D Converter Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 Table 30.9 A/D Converter Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable...
Page 897: Servo Section Electrical Characteristics Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2.6 Servo Section Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 Table 30.10 Servo Section Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.) Reference Values Applicable Item...
Page 898 Reference Values Applicable Item Symbol Pins Test Conditions Unit Note   CFG pin bias voltage   CFG input level AC coupling, C = 1 µF Typ   CFG input kΩ impedance   CFG input V+THCF Rise threshold 2.25 threshold value level...
Page 899: Osd Electrical Characteristics Of Hd6432199, Hd6432198, Hd6432197, And Hd6432196
30.2.7 OSD Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 Table 30.11 OSD Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196 (Reference Value) (Conditions: Vcc = OVcc = 5.0 V, Vss = OVss = 0.0 V, Ta = 25°C unless otherwise specified) Values Applicable Test...
Page 900 Values Applicable Test Item Symbol Pins Conditions Unit Note Character Black CBL1 bias CBL2 CBL3 CBL4 Blue, green, COL1 cyan, red, COL2 magenta, yellow COL3 COL4 White CCL1 CCL2 CCL3 CCL4 Edge brightness level EDG1 EDG2 Button brightness level BTN1 BTN2 Color burst chroma BSTA...
Page 901 Values Applicable Test Item Symbol Pins Conditions Unit Note φ BSTP ± π/4 Chroma hue Colorburst CVout angle φ BLUP ± π Blue (background, φ GRNP ± 7π/4 Green cursor, character) φ CYNP ± 3π/2 Cyan (PAL) φ REDP ± π/2 φ...
Page 902 Values Applicable Test Item Symbol Pins Conditions Unit Note   Oscillation 4/2fscin Crystal stabilizing time 4/2fscout oscillator   Oscillating 4/2fscin M/NTSC 14.31818 frequency 4/2fscout   B,G,H/PAL 17.734475 (17.734476) I/PAL D,K/PAL 4.43-NTSC B,G,H/SECAM L/SECAM D,K,K1/SECAM   N/PAL 14.328225 ...
Page 903: Electrical Characteristics Of Hd64F2199
30.3 Electrical Characteristics of HD64F2199 30.3.1 DC Characteristics of HD64F2199 Table 30.12 DC Characteristics of HD64F2199 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V* , Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Test Item Symbol...
Page 904 Values Test Item Symbol Applicable Pins Conditions Unit Notes  Input low Vcc=2.7 V to –0.3 0.1 Vcc voltage −0.3  5(6, FWE, IC, 0.2 Vcc IRQ0 to IRQ5 −0.3  Vcc=2.7 V to 0.1 Vcc −0.3  SCK1, SI1, FTIA, FTIB, 0.2 Vcc FTIC, FTID, TRIG, TMBI, $'75*...
Page 905 Values Test Item Symbol Applicable Pins Conditions Unit Notes −I   Output SO1, SCK1, PWM1, =1.0mA Vcc–1.0 high PWM2, PWM3, −I   =0.5mA Vcc– Refer- voltage PWM4, PWM14, ence BUZZ, TMO, TMOW, value FTOA, FTOB, PPG0 to −I ...
Page 906 Values Test Item Symbol Applicable Pins Conditions Unit Notes I    µA Input MD0, FWE Vin=0.5 to /output Vcc–0.5V leakage   5(6, ,543 to ,548, ,& Vin=0.5 to current Vcc–0.5V   SCK1, SI1, SDA0, Vin=0.5 to SCL0, SDA1, SCL1, Vcc–0.5V FTIA, FTIB, FTIC, FTID,...
Page 907 Values Applicable Test Item Symbol Pins Conditions Unit Notes   Active Vcc=5V, mode =10 MHz, current High-speed dissipa- mode tion (CPU   Vcc=5V, Reference value operating) =10 MHz, Medium-speed mode (1/64)  Active Vcc=5V, — mode =10 MHz current dissipa- tion...
Page 908 Values Test Item Symbol Applicable Pins Conditions Unit Notes   µA Vcc=2.7V, Watch WATCH 32kHz mode With crystal current oscillator dissipa-   µA Vcc=5.0V, Reference tion 32kHz value* With crystal oscillator   µA X1=V , 32kHz Standby STBY Without crystal mode...
Page 909 Table 30.14 Bus Drive Characteristics of HD64F2199 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C.) Applicable pin: SCL0, SCL1, SDA0, SDA1 Values Test Item Symbol Applicable Pins Conditions Unit Notes −...
Page 910 30.3.2 Allowable Output Currents of HD64F2199 The specifications for the digital pins are shown below. Table 30.15 Allowable Output Currents of HD64F2199 (Conditions: Vcc = 2.7 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C) Item Symbol Value Unit...
Page 911 30.3.3 AC Characteristics of HD64F2199 Table 30.16 AC Characteristics of HD64F2199 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable Test Item Symbol Unit Notes Pins Conditions ...
Page 912 Values Applicable Test Item Symbol Pins Conditions Unit Figure   5(6 pin low level Vcc = 2.7 V to Figure width 5.5 V 30.13   ,543 to ,548, Input pin high level Vcc = 2.7 V to Figure ,&, $'75*, width 5.5 V...
Page 913 4.0V OSC1 φ (Internal) DEXT Note: * The t includes the RES pin Low level width 20 t DEXT Figure 30.12 External Clock Stabilization Delay Timing Figure 30.13 Reset Input Timing TMBI, FTIA, FTIB, FTIC, FTID, RPTRIG Figure 30.14 Input Timing Rev.
Page 914 30.3.4 Serial Interface Timing of HD64F2199 Table 30.17 Serial Interface Timing of HD64F2199 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable Test Item Symbol Unit Figure Pins...
Page 915 SCK1 Figure 30.16 SCI I/O Timing/Clock Synchronization Mode 2.4kΩ LSI output pin 12kΩ 30pF Timing reference level : 2.0V : 0.8V Figure 30.17 Output Load Conditions Rev. 1.0, 02/00, page 912 of 1141...
Page 916 Table 30.18 I C Bus Interface Timing of HD64F2199 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Test Item Symbol Conditions Min Unit Figure  ...
Page 917 SCLH STOS STAH STAS SCLL SDAS SDAH Note: * S, P and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions Figure 30.18 I C Bus Interface I/O Timing Rev. 1.0, 02/00, page 914 of 1141...
Page 918: A/D Converter Characteristics Of Hd64F2199
30.3.5 A/D Converter Characteristics of HD64F2199 Table 30.19 A/D Converter Characteristics of HD64F2199 (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable Item Symbol Pins Test Conditions...
Page 919: Servo Section Electrical Characteristics Of Hd64F2199
30.3.6 Servo Section Electrical Characteristics of HD64F2199 Table 30.20 Servo Section Electrical Characteristics of HD64F2199 (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.) Reference Values Applicable Pins Item Symbol Test Conditions...
Page 920 Reference Values Applicable Item Symbol Pins Test Conditions Unit Note   CFG pin bias voltage   CFG input level AC coupling, C = 1 µF Typ   CFG input kΩ impedance   CFG input V+THCF Rise threshold 2.25 threshold value level...
Page 921: Osd Electrical Characteristics Of Hd64F2199
30.3.7 OSD Electrical Characteristics of HD64F2199 Table 30.21 OSD Electrical Characteristics of HD64F2199 (Reference Value) (Conditions: Vcc = OVcc = 5.0 V, Vss = OVss = 0.0 V, Ta = 25°C unless otherwise specified) Values Applicable Test Item Symbol Pins Conditions Unit Note...
Page 922 Values Applicable Test Item Symbol Pins Conditions Unit Note Character Black CBL1 bias CBL2 CBL3 CBL4 Blue, green, COL1 cyan, red, COL2 magenta, yellow COL3 COL4 White CCL1 CCL2 CCL3 CCL4 Edge brightness level EDG1 EDG2 Button brightness level BTN1 BTN2 Color burst chroma BSTA...
Page 923 Values Applicable Test Item Symbol Pins Conditions Unit Note φ BSTP ± π/4 Chroma hue Colorburst CVout angle φ BLUP ± π Blue (background, φ GRNP ± 7π/4 Green cursor, character) φ CYNP ± 3π/2 Cyan (PAL) φ REDP ± π/2 φ...
Page 924 Values Applicable Test Item Symbol Pins Conditions Unit Note   Oscillation 4/2fscin Crystal stabilizing time 4/2fscout oscillator   Oscillating 4/2fscin M/NTSC 14.31818 frequency 4/2fscout   B,G,H/PAL 17.734475 (17.734476) I/PAL D,K/PAL 4.43-NTSC B,G,H/SECAM L/SECAM D,K,K1/SECAM   N/PAL 14.328225 ...
Page 925: Appendix A Instruction Set
Appendix A Instruction Set Instructions Operation Notation General register (destination) * General register (source) * General register * General register (32-bit register) Multiplication-Addition register (32-bit register) * (EAd) Destination operand (EAs) Source operand Extend register Condition code register N (negative flag) in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 926 Condition Code Notation Symbol Description Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 Always set to 1 − Not affected by the instruction execution result Rev. 1.0, 02/00, page 924 of 1141...
Page 927 Table A.1 Data Transfer Instruction Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code Mnemonic Size States H N Z V C Advanced Mode MOV.B #xx:8,Rd #xx:8→Rd8 — — — — — — MOV.B Rs,Rd Rs8→Rd8 — —...
Page 928 Table A.2 Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code Mnemonic Size States H N Z V C Advanced Mode ADD.B #xx:8,Rd — Rd8+#xx:8→Rd8 — ADD.B Rs,Rd Rd8+Rs8→Rd8 — ADD.W #xx:16,Rd Rd16+#xx:16→Rd16 — ADD.W Rs,Rd Rd16+Rs16→Rd16 ADD.L #xx:32,ERd —...
Page 929 Table A.3 Logic Operations Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States Mnemonic Size H N Z V C Advanced Mode AND.B #xx:8,Rd Rd8∧#xx:8→Rd8 — — — AND.B Rs,Rd Rd8∧Rs8→Rd8 — — — AND.W #xx:16,Rd Rd16∧#xx:16→Rd16 —...
Page 930 Table A.4 Shift Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code Mnemonic States Size H N Z V C Advanced Mode SHAL SHAL.B Rd — — SHAL.B #2,Rd — — SHAL.W Rd — — — —...
Page 931 Table A.5 Bit Manipulation Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States Mnemonic Size H N Z V C Advanced Mode — — — — — BSET BSET #xx:3,Rd — (#xx:3 of Rd8)←1 — —...
Page 932 Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States Mnemonic Size H N Z V C Advanced Mode — — — — — BIAND BIAND #xx:3,Rd C∧ [~(#xx:3 of Rd8)]→C — — — — — BIAND #xx:3,@ERd C∧...
Page 933 Table A.6 Branch Instructions Addressing Mode and Instruction Length (Bytes) No of Operation Execution Operation Code States Mnemonic Size Branch H N Z V C Advanced Mode Condition — — — — — — — BRA d:8(BT d:8) if condition is true then Always —...
Page 934 Table A.7 System Control Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Code Operation States Mnemonic Size H N Z V C Advanced Mode — — — — — TRAPA TRAPA #x:2 — PC→@-SP,CCR→@-SP, 8 [9] EXR→@-SP,<Vector>→PC —...
Page 935 Table A.8 Block Transfer Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code Mnemonic Size States H N Z V C Advanced Mode EEPMOV EEPMOV.B — if R4L≠0 — — — — — — 4+2n * Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6...
Page 936: Instruction Codes
Instruction Codes Rev. 1.0, 02/00, page 934 of 1141...
Page 937 Rev. 1.0, 02/00, page 935 of 1141...
Page 938 Rev. 1.0, 02/00, page 936 of 1141...
Page 939 Rev. 1.0, 02/00, page 937 of 1141...
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Page 945 The following table shows the correspondence between the register field and the general register. Address Register, 32-bit Register 16-bit Register 8-bit Register Register General Register General Register General Field Register Field Register Field Register 0000 0000 0001 0001 0111 0111 1000 1000 1001...
Page 946: Operation Code Map
Operation Code Map Table A.10 shows an operation code map. Rev. 1.0, 02/00, page 944 of 1141...
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Page 950: Number Of Execution States
Number of Execution States This section explains execution state and how to calculate the number of execution states for each instruction of the H8S/2000 CPU. Table A.12 indicates number of cycles of instruction fetch and data read/write during instruction execution, and table A.11 indicates number of states required for each instruction size. The number of execution states can be obtained from the equation below.
Page 951 Table A.11 Number of States Required for Each Execution Status (Cycle) Target of Access On-Chip Supporting Module Execution Status (Cycle) On-Chip Memory 8-bit bus 16-bit bus Instruction fetch S — — Branch address read S Stack operation S Byte data access S Word data access S Internal operation S Rev.
Page 952 Table A.12 Instruction Execution Status (Number of Cycles) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs, Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd...
Page 953 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd...
Page 954 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8...
Page 955 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2 ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B 2n+2 EEPMOV.W 2n+2 EXTS EXTS.W Rd EXTS.L ERd EXTU...
Page 956 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16...
Page 957 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn...
Page 958 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd...
Page 959 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1.
Page 960: Bus Status During Instruction Execution
Bus Status during Instruction Execution Table A.13 indicates execution status of each instruction available in this LSI. For the number of states required for each execution status, see table A.11, Number of States Required for Each Execution Status (Cycle). Interpreting the Table Order of execution Instruction Internal operation...
Page 961 Table A.13 Instruction Execution Status Instruction ADD.B #xx:8,Rd R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd...
Page 962 Instruction BLT d:8 R:W NEXT R:W EA BGT d:8 R:W NEXT R:W EA BLE d:8 R:W NEXT R:W EA BRA d:16 (BT d:16) R:W 2nd Internal R:W EA operation 1 state BRN d:16 (BF d:16) R:W 2nd Internal R:W EA operation 1 state BHI d:16...
Page 963 Instruction BLE d:16 R:W 2nd Internal R:W EA operation 1 state BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M W:B EA NEXT BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M W:B EA NEXT BCLR R:W 2nd R:W 3rd R:B:M EA R:W:M W:B EA #xx:3,@aa:16...
Page 964 Instruction BOIR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BOIR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BIST #xx:3,Rd R:W NEXT BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M W:B EA NEXT BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M W:B EA NEXT...
Page 965 Instruction BNOT Rn @aa:16 R:W 2nd R:W 3rd R:B:W EA R:W:M W:B EA NEXT BNOT Rn @aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M W:B EA NEXT BOR #xx:3,Rd R:W NEXT BOR #xx:3,ERd R:W 2nd R:B EA R:W:M NEXT BOR #xx:3,@aa:8 R:W 2nd...
Page 966 Instruction BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BTST Rn,Rd R:W NEXT BTST Rn,@ERd R:W 2nd...
Page 967 Instruction DIVXU.B Rs,Rd R:W NEXT Internal operation 11 state DIVXU.W Rs,ERd R:W NEXT Internal operation 19 state EEPMOV.B R:W 2nd R:B EAs R:B EAd R:B EAs W:B EAd R:W NEXT EEPMOV.W R:W 2nd R:B EAs R:B EAd R:B EAs W:B EAd R:W NEXT ←...
Page 968 Instruction LDC @ERs+,EXR R:W 2nd R:W NEXT Internal R:W EA operation 1 state LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LDC @aa:32,EXR R:W 2nd...
Page 969 Instruction MOV.W Rs,Rd R:W NEXT MOV.W @ERs,Rd R:W NEXT R:W EA MOV.W R:W 2nd R:W NEXT R:W EA @(d:16,ERs),Rd MOV.W R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA @(d:32,ERs),Rd MOV.W @ERs+,Rd R:W NEXT Internal R:W EA operation 1 state MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA MOV.W @aa:32,Rd R:W 2nd...
Page 970 Instruction MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2 MOVFPE Cannot be used in this LSI. @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation 11 state MULXS.W Rs,Rd R:W 2nd...
Page 971 Instruction ROTR.B Rd R:W NEXT ROTR.B #2,Rd R:W NEXT ROTR.W Rd R:W NEXT ROTR.W #2,Rd R:W NEXT ROTR.L ERd R:W NEXT ROTR.L #2,ERd R:W NEXT ROTXL.B Rd R:W NEXT ROTXL.B #2.Rd R:W NEXT ROTXL.W Rd R:W NEXT ROTXL.W #2,Rd R:W NEXT ROTXL.L ERd R:W NEXT ROTXL.L #2,ERd...
Page 972 Instruction SHLL.L #2,ERd R:W NEXT SHLR.B Rd R:W NEXT SHLR.B #2,Rd R:W NEXT SHLR.W Rd R:W NEXT SHLR.W #2,Rd R:W NEXT SHLR.L ERd R:W NEXT SHLR.L #2,ERd R:W NEXT SLEEP R:W NEXT Internal operation: STC.B CCR,Rd R:W NEXT STC.B EXR,Rd R:W NEXT STC.W CCR,@ERd R:W 2nd R:W NEXT W:W EA...
Page 973 Instruction STMAC MACH,ERd Cannot be used in this LSI. STMAC MACL,ERd SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd R:W 3nd R:W NEXT SUB.L ERs,ERd R:W NEXT SUB #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd...
Page 974: Change Of Condition Codes
Change of Condition Codes This section explains change of condition codes after instruction execution of the CPU. Legend of the following tables is as follows. m = 31: Longword size m = 15: Word size m = 7: Byte size Bit i of source operand Bit i of destination operand Bit i of result...
Page 975 Table A.14 Change of Condition Code Instruc- tion Definition H=Sm-4⋅Dm-4+Dm-4⋅5P07+Sm-4⋅5P07 N=Rm ⋅53 Z=5P⋅5P04⋅ V=Sm⋅Dm⋅5P+6P⋅'P⋅Rm C=Sm⋅Dm+Dm⋅5P+Sm⋅5P − − − − − ADDS ADDX H=Sm-4⋅Dm-4+Dm-4⋅5P07+Sm-4⋅5P07 N=Rm ⋅53 Z=Z'⋅5P⋅ V=Sm⋅Dm⋅5P+6P⋅'P⋅Rm C=Sm⋅Dm+Dm⋅5P+Sm⋅5P − − N=Rm ⋅53 Z=#5P⋅5P04⋅ ANDC Value in the bit corresponding to execution result is stored.
Page 976 Instruc- tion Definition H=Sm-4⋅'P07+'P07⋅Rm-4+Sm-4⋅Rm-4 N=Rm ⋅53 Z=5P⋅5P04⋅ V=6P⋅Dm⋅5P+Sm⋅'P⋅Rm C=Sm⋅'P+'P⋅Rm+Sm⋅Rm N=Rm ⋅53 Z=5P⋅5P04⋅ C: Decimal addition carry N=Rm ⋅53 Z=5P⋅5P04⋅ C: Decimal subtraction borrow − − N=Rm ⋅53 Z=5P⋅5P04⋅ V=Dm⋅5P − − − DIVXS N=Sm⋅'P+6P⋅Dm ⋅63 Z=6P⋅6P04⋅ − − − DIVXU N=Sm ⋅63 Z=6P⋅6P04⋅...
Page 977 Instruc- tion Definition MOVFPE Cannot be used in this LSI. MOVTPE − − − MULXS N=R2m ⋅53 Z=55P⋅55P04⋅ − − − − − MULXU H=Dm-4+Rm-4 N=Rm ⋅53 Z=5P⋅5P04⋅ V=Dm⋅Rm C=Dm+Rm − − − − − − − N=Rm ⋅53 Z=5P⋅5P04⋅ −...
Page 978 Instruc- tion Definition − SHAL N=Rm ⋅53 Z=5P⋅5P04⋅ V=Dm⋅Dm-1+'P⋅'P04 (In case of 1 bit) V=Dm⋅Dm-1⋅Dm-2⋅'P⋅'P04⋅'P05 (In case of 2bits) C=Dm , C=Dm-1 (In case of 1 bit) (In case of 2 bits) − SHAR N=Rm ⋅53 Z=5P⋅5P04⋅ C=D0 , C=D1 (In case of 1 bit) (In case of 2 bits) −...
Page 979: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Addresses Table B.1 Addresses Register Module Address* Name Access Width Name H'0000 H'CFFF H'D000 DGKp DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8 Drum digital filter H'D001 DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0 H'D002 DGKs DGKs15...
Page 980 Register Module Address* Name Access Width Name  H'D028 DFIC DROV DPHA DZPON DZSON DSG2 DSG1 DSG0 Digital filter  H'D029 CFIC CROV CPHA CZPON CZSON CSG2 CSG1 CSG0   H'D02A DFUCR PTON CP/'3 CFEPS DFEPS CFESS DFESS H'D030 DFPR DFPR15 DFPR14...
Page 981 Register Module Address* Name Access Width Name H'D06C DFCRA* ISEL2 CCLR CKSL DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0 HSW timing generator    H'D06C DFCTR* DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0    H'D06D DFCRB DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0 H'D06E CHCR HSWPOL...
Page 982 Register Module Address* Name Access Width Name    H'D098 CTVC Frequency divider H'D099 CTLR CTL7 CTL6 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0  H'D09A CDVC MCGin DVTRG CPS1 CPS0  H'D09B CDIVR1 CDV16 CDV15 CDV14 CDV13 CDV12 CDV11 CDV10 ...
Page 983 Register Module Address* Name Access Width Name H'D10A ICRBH 8/16 Timer X1 H'D10B ICRBL H'D10C ICRCH 8/16 H'D10D ICRCL H'D10E ICRDH 8/16 H'D10F ICRDL   H'D110 TMB17 TMBIF TMBIE TMB12 TMB11 TMB10 Timer B H'D111 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11...
Page 984 Register Module Address* Name Access Width Name H'D13B TMJC 8/16 BUZZ1 BUZZ0 MON1 MON0 TMJ2IE TMJ1IE PS22 Timer J       H'D13C TMJS 8/16 TMJ2I TMJ1I H'D13D H'D147 H'D148 SMR1 STOP CKS1 CKS0 Clock synchronous/ H'D149 BRR1 asynchronous H'D14A...
Page 985 Register Module Address* Name Access Width Name  H'D225 SLINE2 8/16 SENBL2 SFLD2 SLINE24 SLINE23 SLINE22 SLINE21 SLINE20 Data slicer  H'D226 SLINE3 8/16 SENBL3 SFLD3 SLINE34 SLINE33 SLINE32 SLINE31 SLINE30  H'D227 SLINE4 8/16 SENBL4 SFLD4 SLINE44 SLINE43 SLINE42 SLINE41 SLINE40 ...
Page 986 Register Module Address* Name Access Width Name H'FFC3 PDR3 PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30 Port data register H'FFC4 PDR4 PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40 H'FFC5 H'FFC6 PDR6 PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60 H'FFC7 PDR7...
Page 987 Register Module Address* Name Access Width Name H'FFF8 FLMCR1 SWE1 ESU1 PSU1 Flash memory H'FFF9 FLMCR2 FLER SWE2 ESU2 PSU2 H'FFFA EBR1 H'FFFB EBR2 EB15 EB14 EB13 EB12 EB11 EB10           ...
Page 988: Function List
Function List H'D000 to H'D001: Drum Phase Gain Constant DGKp: Drum Digital Filter DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8 DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0 Initial value H'D002 to H'D003: Drum Speed Gain Constant DGKs: Drum Digital Filter DGKs15 DGKs14 DGKs13 DGKs12 DGKs11 DGKs10 DGKs9 DGKs8 DGKs7 DGKs6 DGKs5 DGKs4 DGKs3 DGKs2 DGKs1 DGKs0 Initial value H'D004 to H'D005: Drum Phase Coefficient A DAp: Drum Digital Filter...
Page 989 H'D00A to H'D00B: Drum Speed Coefficient B DBs: Drum Digital Filter DBs15 DBs14 DBs13 DBs12 DBs11 DBs10 DBs9 DBs8 DBs7 DBs6 DBs5 DBs4 DBs3 DBs2 DBs1 DBs0 Initial value H'D00C to H'D00D: Drum Phase Offset DOfp: Drum Digital Filter DOfp15 DOfp14 DOfp13 DOfp12 DOfp11 DOfp10 DOfp9 DOfp8 DOfp7 DOfp6 DOfp5 DOfp4 DOfp3 DOfp2 DOfp1 DOfp0 Initial value H'D00E to H'D00F: Capstan Speed Offset DOfs: Drum Digital Filter DOfs15 DOfs14 DOfs13 DOfs12 DOfs11 DOfs10 DOfs9 DOfs8...
Page 990 H'D016 to H'D017: Capstan Phase Coefficient B CBp: Capstan Digital Filter CBp15 CBp14 CBp13 CBp12 CBp11 CBp10 CBp9 CBp8 CBp7 CBp6 CBp5 CBp4 CBp3 CBp2 CBp1 CBp0 Initial value H'D018 to H'D019: Capstan Speed Coefficient A CAs: Capstan Digital Filter CAs15 CAs14 CAs13 CAs12 CAs11 CAs10 CAs9 CAs8 CAs7 CAs6 CAs5 CAs4 CAs3 CAs2 CAs1 CAs0 Initial value H'D01A to H'D01B: Capstan Speed Coefficient B CBs: Capstan Digital Filter...
Page 991 H'D022 to H'D023: Drum System Phase Delay Initialization Register DZp: Digital filter DZp15 DZp14 DZp13 DZp12 DZp11 DZp10 DZp9 DZp8 DZp7 DZp6 DZp5 DZp4 DZp3 DZp2 DZp1 DZp0 Initial value — — — — H'D024 to H'D025: Capstan System Speed Delay Initialization Register CZs: Digital filter CZs15 CZs14 CZs13 CZs12 CZs11 CZs10 CZs9 CZs8 CZs7 CZs6 CZs5 CZs4 CZs3 CZs2 CZs1 CZs0 Initial value —...
Page 992 H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter Bit : — DROV DPHA DZPON DZSON DSG2 DSG1 DSG0 Initial value : R/(W)* R/(W) R/W : — Drum system gain control bit DSG2 DSG1 DSG0 Description (Initial value) x 16 (x 32)* (x 64)* Invalid (do not set)
Page 993 H'D029: Capstan System Digital Filter Control Register CFIC: Digital Filter Bit : — CROV CPHA CZPON CZSON CSG2 CSG1 CSG0 Initial value : — R/(W)* R/(W) R/W : Capstan system gain control bit CSG2 CSG1 CSG0 Description (Initial value) x 16 (x 32)* (x 64)* Invalid (do not set)
Page 994 H'D02A: Digital Filter Control Register DFUCR: Digital Filter Bit : — — PTON CP/DP CFEPS DFEPS CFESS DFESS Initial value : — — R/W : Drum speed system error data transfer bit 0 Transfer data by NCDFG signal latch. (Initial value) 1 Transfer data at the time of error data write.
Page 995 H'D030 to H'D031: Specified DFG Speed Preset Data Register DFPR: Drum Speed Error Detector DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8 DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0 Initial value H'D032 to H'D033: DFG Speed Error Data Register DFER: Drum Speed Error Detector DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8 DFER7 DFER6 DFER5 DFER4 DFER3 DFER2 DFER1 DFER0 Initial value...
Page 996 H'D038: Drum Speed Error Detection Control Register DFVCR: Drum Speed Error Detector Bit : DFCS1 DFCS0 DFOVF DFRFON DF-R/UNR DPCNT DFRCS1 DFRCS0 Initial value : R/(W) (R)/W (R)/W R/W : Drum lock counter setting bit DFRCS1 DFRCS0 Description Underflow by 1 lock detection (Initial value) Underflow by 2 lock detections Underflow by 3 lock detections Underflow by 4 lock detections...
Page 997 H'D039: Drum Phase Error Detection Control Register DPGCR: Drum Phase Error Detector Bit : — — — DPCS1 DPCS0 DPOVF HSWES Initial value : — — — R/(W)* R/W : Edge select bit Latch at rising edge (Initial value) Latch at falling edge Error data latch signal select bit HSW (VideoFF) signal (Initial value) NHSW (NarrowFF) signal...
Page 998 H'D03A to H'D03B: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Phase Error Detector DPPR15 DPPR14 DPPR13 DPPR12 DPPR11 DPPR10 DPPR9 DPPR8 DPPR7 DPPR6 DPPR5 DPPR4 DPPR3 DPPR2 DPPR1 DPPR0 Initial value H'D03C: Specified Drum Phase Preset Data Register 1 DPPR1: Drum Phase Error Detector Bit : —...
Page 999 H'D052 to H'D053: CFG Speed Error Data Register CFER: Capstan Speed Error Detector CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8 CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0 Initial value *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W *R/W...
Page 1000 H'D058: Capstan Speed Error Detection Control Register CFVCR: Capstan Speed Error Detector Bit : CFCS1 CFCS0 CFOVF CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0 Initial value : R/(W) (R)/W (R)/W R/W : Capstan lock counter setting bit CFRCS1 CFRCS0 Description Underflow by 1 lock detection (Initial value) Underflow by 2 lock detections Underflow by 3 lock detections Underflow by 4 lock detections...

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H8s/2197 Hd6432197 H8s/2196 Hd6432196 H8s/2199f-ztat Hd6432199 ... Show all

Hitachi H8S/2199 Hardware Manual

Section 1 Overview

Cpu

MCU Operating Modes

Power-Down State

Exception Handling

Section 6 Interrupt Controller

Rom

Ram

Clock Pulse Generator

Section 10 I/O Port

Section 11 Timer a

Section 12 Timer B

Section 13 Timer J

Section 14 Timer L

Section 15 Timer R

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Summary of Contents for Hitachi H8S/2199