Sony DTC-670 Service Manual page 46

Pin No. Pin Name
ao
Description
49
50
5 l
52
53
PLVR
PLVF
MSSL
RX
VDD
o
o
I
I
RX APLL comparison signal when extemal comparator is active (Vin)
Not in use
RX APLL comparison signal when extemal comparator is active (Rin)
Not in use
Master/slave setting ("H": master (fixed with the equipment), "L": slave)
Digital input
5 V
54
))
56
57
5 8
TX
AUDR
EXSY
EXSN
F t 2 8
o
I
UO
VO
UO
Digital output
Audio mode/dau recorder mode sening ('H":
Compleæ copy sync signal (2513 - 1O0R Hz)
Complete copy sync signal (2513 - 100/3 Hz)
l2SfsCK (normal)/256fsCK (x2) (DUTY5O)
audio mode, "L": data recorder mode)
59
60
6 t
62
63
F256
F512
ADLF
DALF
XT2O
o
o
I
I
o
256fsCK (normal)/5l 2fsCK (x2) (DUfi 50)
5 l2fsCK (normal)/S I 2fsCK (x2) (DUTY50)
Signal for discriminating whether ADDT serial data is MSB first or LSB first ("H": LSB first)
Signal for discriminating whether DADT serial data is MSB first or LSB first ("H": LSB first)
225792 MHz crystal oscillator ouçut
&
65
66
67
68
xT2r
VSS
XT3O
XT3I
FSEN
o
I
I
I
22.5792 MHz crystal oscillator input
GND
49.l52MHz crystal oscillator output (24.576 MHz in B mode)
49.152MHz crystal oscillator input (24576 MHz in B mode)
F128, BCK, LRCK input/output switch ("H": output)
69
70
7 r
72
73
LRO3
LRO2
LROl
LRCK
wcK
o
o
o
UO
VO
LR02 inversion
LRCK I6BCK delay signal
LRCK 15BCK delay signal
fs (normal)/2fs (x2) ("L": L-CH, "H": R-CH)
2fs (normal)/4fs (x2) (input mode only for testing)
74
76
77
7 8
XBCK
BCK
ADDT
DADT
DADO
o
UO
I
o
I
BCK inversion
64fs (normal)/l 28fs (x2)
Serial AD data (complement of 2)
Serial DA data (complement of 2)
Digital output (DA) data input (normally connected to DADT)
79
80
8 l
82
83
ADDI
ADDN
ERRI
ERRF
MUTG
o
I
I
o
o
Digital input (AD) data outpul (normally connected to ADDN)
Digital input (DA) data input
Digital ouçut V-FLAG data input (normally connected to ERRF)
Signal output for discriminating whether or not DADT has interpolated data ("H": interpolated data)
Error correction status monitor trigger
84-89
90
9r,92
93-100
D7.D2
vss
DI, DO
AOGAOT
r/o
UO
VO
RAM data bus D7-D2
GND
RAM data bus Dl, D0
RAM address A0GA07