Yamaha tx7 Service Manual page 13

t-
X
I-
P22
(in)
P23
(in)
P24
(out)
P25
(out)
P26
(out)
P27
(out)
•
Port 5
P50
(in)
P51
(in)
P52
(in)
P53
(in)
P54, 55
P56
(in)
P57
(in)
•
Port
6
Port
6 P
60
LCD.
This
is
a
500 Khz
clock input
which
de-
termines the MIDI transmission speed.
The
clock
is
internally divided
by
16.
Therefore,
MIDI
transmission
is
31.25
K
baud.
Receives
MIDI
messages.
Sends
MIDI
messages.
This sends
a signal
to the
RS
terminal of
the LCD. This
signal tells
the
LCD whether
the data
from
port 6
P60
~
P67
is
an
in-
struction or data to be displayed.
"High"
means
data to be displayed.
This determines input or
output
of
LCD
data. "High": read.
"Low":
write.
Finalize
LCD
data. Data finalized
when
down.
Condition of
"Low"
switch
Condition of
"
" switch
Condition of " "
switch
Condition of "High" switch
Not used
Battery voltage condition
Read data from cassette
~
P
67
transmit instructions
and data to the
• Bus
The
address bus
is
A
0
—
A
ls .
The
data bus
is
D
0
~
D
7 .
• BA
Bus av
ailable
terminal.
When
the
MPU
has received
a
HALT
and the bus
is
free, this terminal
will
be "High".
Not
used in this circuit.
•
UR
This indicates that the data
bus
is
carrying the op code
of an instruction.
•
R/W
When
the
MPU
is
reading, this
is
"High".
When
writing,
this
is
"Low".
•
WR
When
the
MPU
is
writing, this
is
"Low".
• RD
When
the
MPU
is
reading, this
is
"High".
•
E
'
This enables a
system dock
to be sent.
2)
Tone generator section
The tone
generator section
is
the
same
as
that of the
DX7.
The
EGS
and
OPS
use the
same
1C and function
in
the
same
way
as the
DX7. The EGS
is
master and the
OPS
is slave.
All the
OPS
does
is
to perform
FM
calculations
on
the data
sent to
it
from
the
EGS (FM
calculation parameters ECi
~
EC„,
Pi
—
F
14
)
according to the algorithm
to
which
it is
set.
•
EGS
This
is
an
acronym
for
Envelope
Generator of
Synthe-
sizer. This
is
the LSI that
reads voice data
(rate, level,
key code
etc)
from
the
MPU
into its
internal registers
and produces
(digital)
envelope shape information
according
to the
key on/off
signals it
receives
from
the
MPU.
It
also
produces
(digital)
frequency data for the
key which has been pressed.
Along with the key
on (KON)
data,
the
volume
envelope
date
ECi
~ ECu
and
frequency data Fi
—
F 14 are sent
to the
OPS,
in
synchronization with
the system sync
signal
SYNC
(92Y96).
• Vdd,
Vss
Vdd
is
+5V power supply, Vss
is
ground
• RES
This terminal resets
the EGS.
• SYNC
Input terminal for synchronizing the
OPS.
(92Y96)
• CE
Pulse input terminal for enabling reception
of data
from
the
MPU.
• WFf Pulse input terminal for writing
data
from
the
MPU
into internal registers. In the
TX7,
this is
connected to
GND.
•
A
0
~
A
7
Address input terminal for specifying
internal registers.
• Do
~
D
7
Data input terminals
•
Fi
-F
14 Parallel
output for
frequency data
of each
channel
• ECi
~
Parallel
output for volume data of each
EC
i2
channel
• OE
Data output
control terminal,
but
in
the
TX7
is
connected to
GND.
• KON
Output
terminal for
key
ON
data of the
specified channel
•
01. 02
System clock input terminals
• OPS
This
is
an
acronym
for Operator of Synthesizer. By
performing
FM
calculations
on
the
volume
envelope,
frequency and
KON
data sent to
it
from
the
EGS
and
on
the data already stored
in
the
OPS
registers
(algorithm
NO., feedback
level),
the
OPS
produces audio data
(in
12
bit digital
form).
The
data that the
OPS
receives directly from the
MPU
is
2 bytes
as follows.
Mode
(operation
mode
of OPS)
1
byte
Algorithm
no.
(upper 5
bits)
.
.
Feedback
level (lower
3
bits)
Y e
The
terminal
WR
writes to the
OPS, and
has
been
assigned
to addresses
5800
(H)
~
5801 (H). Since the address line
A
0
is
connected to the data set terminal
DS
of the OPS,
the
OPS mode
selector
is
A
0
- "Low",
ie.
5800
(H).
When
A
0
= "High",
ie.
5801 (H) specifies data register
(algorithm no., feedback
level).
The
output data of the
OPS
is
12
bit.
However, to
make
this
the equivalent of 14
bit,
the lower
levels
are ex-
panded
2, 4,
and 8
times respectively.
To
return
this
to
the original valve, shift data (SF
0
~SF
3
)
is
sent out.
SF
0 :
1
times,
SF
2
:
1/2 times,
SF
2
:
1/4 times,
SF
3 :
1/8 times.
Vdd, Vss Vdd
is
+5V
power supply, Vss
is
ground
• DS
This
determines whether data input Do
~
D
7
is
mode or algorithm no and feedback.
Mode
is
"L".
•
WR
Input terminal indicates
whether
to write
the data atD
0
—
D? into an internal register.
• SH!
,
SH
2
Sample and hold output terminal
•
SYNC
Output terminal for
92Y96
sync signal
•
Fi
~
F 14 Parallel
inputs for frequency data
from EGS
•
DA
t
~
Digital
audio
parallel
outputs
DA
l2
• SF
0
~
Shift data outputs (to restore
expanded
SF
3
output data)
• ECi
—
Parallel
inputs for
volume envelope
data
£C
l2
from the
EGS
•
KON
Key
ON
data input for the selected channel
• D
0
D
7
Inputs for
mode,
algorithm
number, and
feedback level
from
the
MPU
• 0i,02 System clock inputs
When 4800
(H)
comes
up,
IC28
(data latch) will latch the
data on the data bus
line.
(At this time,
it
latches only
the upper 6
bits
of the data bus.)
This data that
has been latched
is
sent out of the
o
terminal
as
"High" +5V,
"Low"
0V, and
is
input
to
rader resistance
RMi. This voltage passes through IC35 (which makes up
the
low
pass filter)
and appears
at
pin
1
of IC35.
It
is
divided
by
a
270ft and
a
22ft
resistors
and added to pin 3
of the
VCA
IC38. This controls the
VCA
which controls
the
volume
of
the analog
signal
sent
from
the tone generator
section.
When
the control voltage of the
VCA
is
0V, the
volume
is
greatest
and
when
it is
0.37V, the volume
is least.
As you can
see
from the software flow diagram
o,
battery
voltage
check
is
performed
when
the power
is
turned on.
A
voltage identical to the
volume control voltage
is
sent to
pins of IC35.
The output of
that
is
sent to
pin 3 of 1C18
(battery voltage converter)
on
the
DM
board.
When
the
power
is
turned on, the battery
check
routine will be
entered, and pin 7 of
IC35
has
been programmed
to rise
from OV. As long as the battery voltage
is
higher than this
voltage, the output of IC18 pin 7 will
be "High". When
this
voltage becomes higher than the battery boitage, the
output
of pin 7
will
reverse to
"Low". The
MPU
is
checking
for
this,
and
when
the battery voltage
is less
than 2.3V,
the
LCD
will
show
"CHANGE BATTERY".
3)
D/A converter section
The
1
2 bit digital data
from the
OPS
is
sent to the
DAC
IC24 and converted into
an analog
signal.
This 12
bit digital
data has
been expanded
inside
the OPS, so the IC26 and the
connected resistances will return
it
to
the original
level.
This
is
controlled
by
the shift
data sent from the
OPS
(SF
0
—
SF
3 ),
which
is
sent at the
same time
as
the 12 bit digital
data.
The
shift data
is
as follows.
When the data sent to the
DAC
has been shifted
1
time,
SF
0
sends
"High".
When
the data sent to the
DAC
has been shifted 2 times,
FSi sends
"High".
When the data sent to the
DAC
has been shifted
4
times,
SF
2
sends
"High".
When
the data sent to the
DAC
has been shifted 8 times,
SF
3
Sends "High".
At
this
point, the level has
been
corrected,
but
it is still
not
a
true analog
waveform.
Until the digital
audio data comes
into the
sample and hold
circuit,
it is
being outplut
in
steps
(first
note,
second
note, third note,
. . .
).
Controlled
by the sampling signals
SH
2
and SH
2
,
the IC27 samples
the digital
audio
signal.
A
120 pf caoacitor
holds the
level
and converts
it
into an analog signal. (SH
2
samples
the first
through eighth notes,
SH
2
samples
the ninth through
sixteenth notes.) This
waveform
still
has
a stair-step
shape,
so
it
is
put through
a
low-pass filter to
become
a
true analog
waveform. This signals
volume
is
controlled by the
VCA,
and
it is
sent out.
4)
Volume
control
and
battery voltage
check circuitry
Volume
is
controlled by the
VCA
IC38. The volume
is
determined
by the following information.
o
Panel switch preset
volume
. .
.
fLowH
)
! j
HIGH!
o
Attenuation (function
mode).
.
.ATTENUATION
0~7
o
Data entry volume control
o Control change.
. .
control
number
7
These two are
~| mutually
exclu-
I
sive; ie
only
one
at a
time.
5)
Power supply
The power
supply used in the
TX7
is
of the type
know
as
RCC
(Ringing
Choke
Converter).
The
basic
RCC
circuit
is
shown
in
diagram
10. Tr
2
is
a switching transistor.
When
this transistor
is
ON,
energy accumulates
in
inducter Li of
transformer T,
and
when OFF,
the
accumulated
energy
is
released to side
L
3 .
As
the transistor
Tr
2
repeats this
swithcing,
power
is
sent out.
R
2
is
a
base current
limiting
resistor for
Tr
lt
Ri
is
a starting resistor,
and
when
the
resistance
is
low, Tri
will start easier.
Transformer
T
is
an oscillating
transformer, and
isolates the
primary and
secondary.
You may
calculate
the energy accumulated
in
transformer
T
(inductor) using the following equation.
U *
(Vin
2 xTon 2
)/2Li
U
* accumulated energy
Lj *
self
inductance
Vin * input
voltage
Ton * transformer
ON
time
SW
i-
;
Diagram
1
0
The operation of the
RCC
circuit
is
as follows.
1.
When you
turn
on
SW
in
diagram
10,
current flows
through
R
2
to
the base of Tr
2
.
This turns the Tri on,
and
current flows
in
Li
,
inducing
voltage in
L
2 .
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