Service Schematics; Nc Point(Top View); Pin Assignment Diagram - Samsung GT-i9100 Service Manual

8-4. Service Schematics

- NC Point(Top View)

UCP400
: NC
2.1 Pin Ass ignm ent Diagr am
1 2 3 4 5 6
VDD XEIN VDD
A VSS VSS VSS
1_E T_23 Q_E2 Q_M2
XEIN XEIN XEIN XEIN XEI
B VSS
T_22 T_24 T_30 T_17 NT_8 Q_M2
VDD XEIN XEIN XEIN XEIN XEI
C
2_E T_13 T_31 T_27 T_12 NT_2 Q_M2
XEI XEIN XEIN XEIN XEIN XEI
D
NT_6 T_26 T_18 T_25 T_14 NT_5 Q_M2
VDD XEIN XEIN XEIN XEI XEI
E
Q_E1 T_20 T_29 T_21 NT_4 NT_0 Q_M2
XEIN XEIN XEIN XEIN XEIN VDD
F
T_28 T_11 T_16 T_15 T_10 Q_M 2 Q_M2
VDD XEI XEI XEIN XEI VDD
G
Q_E1 NT_3 NT_9 T_19 NT_7 Q_M 1
VDD VDD VDD VDD VDD VDD
H
Q_M1 Q_M 1 Q_M1 Q_M 1 Q_M 1 Q_M 1
VDD
J VSS XOM_3 XOM _2 XOM_5 XOM _4
Q_M 1
VDD XCL VDD
K XOM_0 XOM _6 XOM_1
Q_E1 KOUT Q_M 1
XNWR XPWR XNRS XM1 VDD
L VSS
ESET RGTON TOUT VREF Q_M 1
XGNSS_
VDD18 XPS XNR VDD
M XXTI RF_RST
_TS HOLD ESET Q_M 1
N
VDD XGNSS XGNS XGNSS XGNSS VDD
N
Q_E1 _EPOCH S_SCL _M CLK _IM AG Q_M 1
XGNSS_
XGNSS_ XGNSS_ XGNSS VDD
P VSS RTC_OU
GPIO_2 CLKREQ _ISIGN Q_M 1
T
VDD VDD VDD VDD VDD VDD
R
_ARM _ARM _ARM _ARM _ARM _ARM
VDD VDD VDD VDD VDD VDD
T
_ARM _ARM _ARM _ARM _ARM _ARM
XGNSS XGNSS_ XGNS VDD3
U VSS XM 1ZQ
_QM AG GPIO_4 S_SDA 3_ABB
POP_VR
VDD XGNSS XGNSS_ VSS_ VDD11
V E
1_E _SYNC GPIO_3 APLL _APLL
F_DQ_E1
XGNSS_ XGNSS_ XGNSS_ VSS_ VDD11
W VSS
GPIO_5 GPIO_6 GPIO_1 M PLL _M PLL
VDD XGNSS_ XGNSS_ XVPLL VSS_ VDD11
Y
2_E GPIO_7 GPIO_0 FILTER VPLL _VPLL
XTSEXT XUHOS XGNSS XEPLL VSS_ VDD11
AA
_RES TDATA2 _QSIGN FILTER EPLL _EPLL
VDD XUHOS XEFFSO VDD11H VSS12 VDD12
AB
Q_E1 TDATA1 URCE_0 _UHOST _UHOST _UHOST
XUHOST
XUHO XUHO VSSH_ VSSAC VDD33
AC STROBE
STDP STDM UHOST _UHOST _UHOST
2
XUHOST
XUOT VSSD_ VSSA_ VDD11
AD VSS STROBE
GVBUS UHOST UHOST _UHOST
1
VDD XUOT XUHOS VSSAC VSSA VDD33 VDDQ
AE
Q_E1 GREXT TREXT _UOTG _UOTG _UOTG _SYS0
XUO XUO XUO VDD VSSD VDDQ VDD11
AF
TGDP TGDM TGID _RTC _UOTG _CKO _UOTG
VDD XI2S0 XI2S0 XRTC VDDQ_ VDDQ_ XM0AD
AG
Q_E1 SDO_1 SDO_0 CLKO CKEM 1 CKEM2 DR_13
XUS XUS XI2S XI2S XI2S0 XRT
AH
BXTI BXTO 0SCLK 0SDI SDO_2 CXTO CXTI
VDD XI2S XI2S0 XM0 XM 0F XM0AD
AJ VSS
2_E 0LRCK CDCLK FCLE RNB_2 DR_11
VDD VDD XM 0 XSAT
AK VSS VSS VSS
1_E Q_E1 FALE ARX2P
1 2 3 4 5 6
7 8 9 10 11 12 13 14
VDD VDD XM DM A XM DMA VDD XM DM D XMDMD
VSS VSS
Q_E2 DDR_2 DDR_0 Q_E2 ATA_0 ATA_6
POP_VR
VDD XADC XADC XADC XM DMA XMDM A XM DM A XM DM D
AIN_4 AIN_8 AIN_3 DDR_6 DDR_7 DDR_13 ATA_5
F_DQ_E2
VDD XADC XADC XADC XM DMA XMDM A XM DM A XM DM D XMDMD
AIN_5 AIN_0 AIN_9 DDR_5 DDR_12 DDR_10 ATA_13 ATA_3
VDD XADC XADC XADC XM DMA XMDM A XM DM A XM DM D XMDMD
AIN_1 AIN_7 AIN_2 DDR_4 DDR_9 DDR_1 ATA_1 ATA_10
VDD XEI XADC XM 2 XM DMA XMDM A XM DM A XM DM D XMDMD
NT_1 AIN_6 VREF DDR_3 DDR_8 DDR_11 ATA_7 ATA_9
VDD VDD VDD VDD VDD VDD VDD VDD VDD
Q_M 2 Q_M 2 Q_M 2 Q_M 2 Q_M 2 Q_M 2 Q_M 2 Q_M 2
VSS VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD
VSS
_ARM _ARM _ARM _ARM _ARM _ARM
VDD VDD VDD VDD VDD VDD
VSS
_ARM _ARM _ARM _ARM _ARM _ARM
VDD VDD
VSS VSS VSS VSS VSS
_ARM _ARM
VDD VDD VDD VDD VDD VDD
VSS
_ARM _ARM _ARM _ARM _ARM _ARM
VDD VDD VDD VDD
VSS
_ARM _ARM _ARM _ARM
VDD VDD VDD VDD VDD
_ARM _ARM _ARM _ARM _ARM
VDD VDD VDD VDD VDD
_ARM _ARM _ARM _ARM _ARM
VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VSS VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VDD_ VDDQ VDDQ VDD11 VDD33 XM0A VDD XM0F
ALIVE _SYS1 _AUD1 D_SATA A_SATA DDR_3 _INT RNB_1
VDDQ XM0A VDDQ VDD11 VDD11 XM 0AD VDD VDDQ
_KEY DDR_7 _GPS0 T_SATA A_SATA DR_14 _INT _GPS1
XM 0AD XM 0C XM0AD XSATA XSATA XM0A VDD XM0A
DR_15 SN_1 DR_12 REFRES ATEST DDR_6 _INT DDR_2
XRT XM 0AD XM0A XM 0A XM 0A XM 0A XM 0B VDD XM0F
DR_10 DDR_4 DDR_9 DDR_1 DDR_5 EN_1 _INT RNB_0
XM 0A POP_ XM 0B XM 0A XM 0C VDD XM 0W
VCC _O
DDR_8 CEB_O EN_0 DDR_0 SN_2 _INT AITN
XSAT XSAT XSAT XSATAR XSATAR VDD
VSS VSS
ARX2M ATX2M ATX2P EFCLKP EFCLKM _INT
7 8 9 10 11 12 13 14
Fig ure 2-1 S5PC210 Pin Map(756-FCMSP) Top View
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This Document can not be used without Samsung's authorization
15 16 17 18 19 20 21 22 23
XM DM D XM DM D XM D VDD XVV XVV XVV
VSS
ATA_8 ATA_14 M RN Q_E2 D_10 DEN D_0
XM DM D XM DM D XM DM XVV XVV XVV XVVSY XVV
E
ATA_15 ATA_11 ADVN D_3 D_14 D_1 NC_LDI SYNC
XM DM D XM D XVV XVV XVV XVV XVV XVV
ATA_2 M CSN D_9 D_6 CLK D_4 D_22 D_23
XM DM XM D XVV XVV XVV XVV XVV XVV
IRQN M WEN D_15 D_5 D_7 D_21 D_8 D_19
XM DM D XM DM D XVV XVV XVV XVV VDDQ XVV
ATA_4 ATA_12 D_13 D_20 D_17 D_11 _EXT1 D_12
VDD3 VSS VDDQ_ XVV XVV VDDQ VDDQ
XM 2ZQ
3_ADC _ADC MODEM D_16 D_18 _EXT2 _EXT0
VDD
VSS VSS VSS VSS VSS VSS
_INT
VDD VDD VDD VDD VDD
VSS VSS
_INT _G3D _G3D _G3D _G3D
VDD VDD VDD VDD VDD
VSS VSS
_INT _G3D _G3D _G3D _G3D
VDD VDD
VSS VSS VSS VSS VSS
_INT _G3D
VDD VDD VDD VDD VDD
VSS VSS
_INT _G3D _G3D _G3D _G3D
VDD VDD VDD VDD VDD
_G3D _G3D _G3D _G3D _G3D
VDD
VSS VSS VSS VSS
_G3D
VDD VDD VDD VDD VDD
_G3D _G3D _G3D _G3D _G3D
VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VDD VDD
VSS VSS VSS VSS VSS
_INT _INT
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
VDD VDD VDD VDD VDD VDD
VSS
_INT _INT _INT _INT _INT _INT
XM 0 XM0D VDD VDD XMM C1 XMM C0 XMM C XMM C
OEN ATA_2 Q_M 0 Q_M 0 DATA_1 DATA_3 0CMD 3CLK
XM 0F XM0D XM 0D XM0D XMM C1 VDDQ_ VDDQ VDDQ
RNB_3 ATA_1 ATA_7 ATA_6 DATA_3 MM C01 _MM C3 _MM C2
XM 0C XM0D XM 0D XM 0DA XM 0D XMM C XMM C0 XMM C0
SN_0 ATA_9 ATA_8 TA_14 ATA_3 1CM D DATA_2 DATA_0
XM 0 XM 0DA XM0DA XM0D XM0DA XMM C1 XMM C XMM C3
WEN TA_11 TA_10 ATA_0 TA_15 DATA_0 0CDN DATA_2
XM 0C XM 0DA XM 0D XM 0DA XM 0D XMM C1 XMM C0 XMM C
SN_3 TA_12 ATA_4 TA_RDN ATA_5 DATA_2 DATA_1 0CLK
VCC VCC XM0DA XMM C VCC
VCC _O VSS VSS
Q_O Q_O TA_13 1CDN Q_O
15 16 17 18 19 20 21 22 23
8-67
Level 3 Repair
24 25 26 27 28 29 30
XVSY VDD XUT VDD
VSS VSS VSS A
S_OE Q_E2 XD_3 2_E
XSPI XUT XUCT XSPI XSPIM VDD
VSS B
CSN_1 XD_2 SN_2 CLK_1 OSI_1 1_E
XSPI XURT XUR XSPI XSPIM XUR XURT
C
CSN_0 SN_2 XD_0 CLK_0 ISO_0 XD_1 SN_1
XVH XSPIM XURT XPWMT XPWM T XHDM XHDM
D
SYNC OSI_0 SN_0 OUT_2 OUT_0 IXTO IXTI
XVV VDDQ XSBU XUT XPWM T XHDM XHDM
E
D_2 _SBUS SCLK XD_0 OUT_3 ITX2P ITX2N
XSPIM VDDQ XSBU XUT XPWM T XHDM XHDM
F
ISO_1 _AUD0 SDATA XD_1 OUT_1 ITX1P ITX1N
VDD33_H
VSS_HD XUCT XUCT XHDM XHDM
DMI_OS G
M I_OSC SN_0 SN_1 ITX0P ITX0N
C
VDD11_H VSS_ XUR XUR XHDM XHDM
H
DM I_PLL HDM I XD_3 XD_2 ITXCP ITXCN
POP_VR
VDD11 VSS_ XHDM XI2S2
E VSS J
_HDM I HDM I IREXT CDCLK
F_CA_E1
XI2C XI2S XI2S XI2S XI2S VDD
K
0SCL 2LRCK 1SDO 1SCLK 1SDI 2_E
XI2C VDD33 XI2S XI2S1 XI2S VDDC
L
0SDA A_DAC 1LRCK CDCLK 2SDO A_E1
VDD3 VSSA XI2C XI2S XMIP XM IP
M
3_DAC _DAC 1SCL 2SDI IM DN0 IM DP0
VDD3 VSS XI2C XI2S XMIP XM IP
N
3_ABB _DAC 1SDA 2SCLK IM DN1 IM DP1
XDAC XDAC POP_ VDDC XM IPI XM IPI
P
IREF VREF ZQ_E1 A_E1 M DNCLK MDPCLK
XDAC VDDQ XDA VDD XMIP XM IP
R
COM P _LCD COUT 1_E IM DN2 IM DP2
XCID XCID XCID XMIP XM IP
VSS T
ATA_5 ATA_2 ATA_0 IM DN3 IM DP3
VDD11_ POP_VR
VDD18 XCID XMIP XM IP
M E U
_MIPI ATA_3 ISDN0 ISDP0
IPI_PLL F_CA_E2
VSS_ VDD11 XM IPIVR POP_ XMIP XM IP
V
MIPI _M IPI EG_0P4V ZQ_E2 ISDN1 ISDP1
VSS_ VDD11 XCIF VDD XM IPI XM IPI
W
MIPI _M IPI IELD 2_E SDNCLK SDPCLK
VSS_ VDD11 XCID XCI XMIP XM IP
Y
MIPI _M IPI ATA_7 PCLK ISDN2 ISDP2
VDD11_
VDDQ XCID XCI XMIP XM IP
M I AA
_CAM ATA_4 HREF ISDN3 ISDP3
PI2L_PLL
VSS_M VDD11_ XCIV XM IPI XM IPI
VSS AB
IPI2L M IPI2L SYNC 2LM DN0 2LM DP0
XM IPI2L XM IPI2 XM IPI2
VSS_M VDD11_ VDDC
V LM DNCL LM DPCL AC
IPI2L M IPI2L A_E2
REG_0P4 K K
VDD18_ XCIC XCID VDD XM IPI XM IPI
AD
M IPI2L LKENB ATA_6 1_E 2LM DN1 2LM DP1
XUHOST
XUHOS XCID XM IPI XM IPI
VSS XJTDO OVERCU AE
TPWREN ATA_1 2LSDN0 2LSDP0
R
XM IPI2 XM IPI2
VDDQ VDDQ XJT
XJTCK XJTM S LSDNCL LSDPCL AF
_SYS0 _CAM RSTN
K K
XMM C XMM C3 XMM C2 XUOTGD XM IPI XM IPI
XJTDI AG
3CDN DATA_1 DATA_1 RVVBUS 2LSDN1 2LSDP1
XMM C3 XMM C3 XMM C2 XMM C XJDB POP VDD
AH
DATA_0 DATA_3 DATA_0 2CDN GSEL _TQ1 2_E
XMM C XMM C2 XMM C2 XMM C POP VDD
VSS AJ
1CLK DATA_3 DATA_2 2CM D _TQ0 1_E
XMM C XMM C VDDC
VSS VCC _O VSS VSS AK
3CM D 2CLK A_E2
24 25 26 27 28 29 30