Lvds Receiver Circuit Example (Single Output) - Sony fcb-ev7500 Technical Manual

LVDS receiver circuit example (Single output)

R613
10k
25V
0.1u
C608
25V
0.1u
C610
25V
0.1u
C612
25V
0.1u
C613
• No.1 and 2 of S601 adjust the signal delay. No.3 selects whether to input the rising edge or falling edge of the
signal.
1
PGND_1
2
PVCC_2
3
FB602
RESERVED
4
PDWN
5
MODE0
6
MODE1
7
DK
8
R/F
9
OE
10
MODE2
11
MAP
12
VCC_12
13
GND_13
14
R20
15
R21
16
R22
17
R23
18
R24
19
R25
20
R26
21
VCC_21
22
GND_22
23
R27
24
R28
25
R29
26
G20
27
G21
28
VCC_28
29
VCC_29
30
GND_30
31
G22
32
G23
33
G24
34
G25
35
G26
36
G27
108 25V
0.1u
PGND_108
C607
107
PVCC_107
106
VCC_106
105
CONT12
104
CONT11
103
DE
102
VSYNC
101
HSYNC
100
B19
99
B18
25V
98
0.1u
GND_98
C609
97
VCC_97
96
B17
95
B16
94
B15
93
B14
92
B13
91
B12
90
B11
25V
89
0.1u
GND_89
88 C611
VCC_88
87
B10
86
G19
85
G18
84
G17
83
G16
82
G15
25V
81
0.1u
GND_81
C614
80
VCC_80
79
G14
78
G13
77
G12
76
G11
75
G10
74
R19
73
R18
FB603
Specifications